TL16C554 Datasheet, PDF (13/33 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENT

RXx
Sample
Clock
INTx
(time-out or
trigger level)
Interrupt
INTx
Interrupt
IOR
(RD LSR)
TL16C554, TL16C554I
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS165D – JANUARY 1994 – REVISED JULY 1998
PARAMETER MEASUREMENT INFORMATION
Stop
td9 (see Note A)
50%
50%
Top Byte of FIFO
50%
50%
tpd4
td9
tpd4
Active
50%
(FIFO at or above
trigger level)
(FIFO below
trigger level)
IOR
(RD RBR)
Active
50%
Previous BYTE
Read From FIFO
NOTE A: This is the reading of the last byte in the FIFO.
50%
Active
Figure 11. Receiver FIFO After First Byte (After RDR Set) Waveforms
IOR
(RD RBR)
RXx
Stop
50%
Active
(see Note A)
Sample
Clock
td9
(see Note B)
RXRDY
50%
50%
tpd5
NOTES: A. This is the reading of the last byte in the FIFO.
B. If FCR0 = 1, then td9 = 3 RCLK cycles. For a time-out interrupt, td9 = 8 RCLK cycles.
Figure 12. Receiver Ready Mode 0 Timing Waveforms
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