TL16C554 Datasheet, PDF (30/33 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENT

TL16C554, TL16C554I
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS165D – JANUARY 1994 – REVISED JULY 1998
PRINCIPLES OF OPERATION
scratchpad register
The scratch register is an 8-bit read/write register that has no affect on either channel in the ACE. It is intended
to be used by the programmer to hold data temporarily.
TXRDY operation
In mode 0, TXRDY is asserted (low) when the transmit FIFO is empty; it is released (high) when the FIFO
contains at least one byte. In this way, the FIFO is written with 16 bytes when TXRDY is asserted (low).
In mode 1, TXRDY is asserted (low) when the transmit FIFO is not full; in this mode, the transmit FIFO is written
with another byte when TXRDY is asserted (low).
External
Clock
Driver
XTAL1
Optional
Driver
Optional
Clock
Output
XTAL2
VCC
Oscillator Clock
to Baud
Generator Logic
C1
RP
C2
XTAL1
Crystal
RX2
XTAL2
VCC
Oscillator Clock
to Baud
Generator Logic
CRYSTAL
3.1 MHz
1.8 MHz
TYPICAL CRYSTAL OSCILLATOR NETWORK
RP
1 MΩ
RX2
1.5 kΩ
C1
10 – 30 pF
1 MΩ
1.5 kΩ
10 – 30 pF
C2
40 – 60 pF
40 – 60 pF
Figure 17. Typical Clock Circuits
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