TL16C554 Datasheet, PDF (28/33 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENT

TL16C554, TL16C554I
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS165D – JANUARY 1994 – REVISED JULY 1998
PRINCIPLES OF OPERATION
programmable baud rate generator (continued)
Table 11. Baud Rates Using an 16-MHz Clock
BAUD RATE
DESIRED
50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
56000
128000
256000
512000
1000000
DIVISOR (N) USED TO
GENERATE 16 × CLOCK
20000
13334
9090
7434
6666
3334
1666
834
554
500
416
278
208
138
104
52
26
18
8
4
2
1
PERCENT ERROR DIFFERENCE
BETWEEN DESIRED AND ACTUAL
0
0.00
0.01
0.01
0.01
– 0.02
0.04
– 0.08
0.28
0.00
0.16
– 0.08
0.16
0.64
0.16
0.16
0.16
– 0.79
– 2.34
– 2.34
– 2.34
0.00
receiver
Serial asynchronous data is input into the RXx terminal. The ACE continually searches for a high-to-low
transition from the idle state. When the transition is detected, a counter is reset and counts the 16 × clock to
7 1/2, which is the center of the start bit. The start bit is valid when the RXx is still low. Verifying the start bits
prevents the receiver from assembling a false data character due to a low going noise spike on the RXx input.
The LCR determines the number of data bits in a character (LCR0, LCR1). When parity is enabled, LCR3 and
the polarity of parity LCR4 are needed. Status for the receiver is provided in the LSR. When a full character is
received including parity and stop bits, the data received indicator in LSR0 is set. The CPU reads the RBR, which
clears LSR0. If the character is not read prior to a new character transfer from the RSR to the RBR, the overrun
error status indicator is set in LSR1. If there is a parity error, the parity error is set in LSR2. If a stop bit is not
detected, a framing error indicator is set in LSR3.
In the FIFO mode operation, the data character and the associated error bits are stored in the receiver FIFO.
If the data into RXx is a symmetrical square wave, the center of the data cells occurs within ± 3.125% of the actual
center, providing an error margin of 46.875%. The start bit can begin as much as one 16 × clock cycle prior to
being detected.
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