TL16C554 Datasheet, PDF (24/33 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENT

TL16C554, TL16C554I
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS165D – JANUARY 1994 – REVISED JULY 1998
PRINCIPLES OF OPERATION
modem status register (MSR)
The MSR provides the CPU with status of the modem input lines for the modem or peripheral devices. The MSR
allows the CPU to read the serial channel modem signal inputs by accessing the data bus interface of the ACE.
It also reads the current status of four bits of the MSR that indicate whether the modem inputs have changed
since the last reading of the MSR. The delta status bits are set when a control input from the modem changes
states and are cleared when the CPU reads the MSR.
The modem input lines are CTS, DSR, and DCD. MSR4 – MSR7 are status indicators of these lines. A status
bit = 1 indicates the input is low. When the status bit is cleared, the input is high. When the modem status interrupt
in the IER is enabled (IIR3 is set), an interrupt is generated whenever MSR0 – MSR3 is set. The MSR is a priority
4 interrupt. The contents of the MSR are described in Table 7.
D Bit 0: MSR0 is the delta clear-to-send (∆ CTS) bit. DCTS indicates that the CTS input to the serial channel
has changed state since it was last read by the CPU.
D Bit 1: MSR1 is the delta data set ready (∆ DSR) bit. ∆ DSR indicates that the DSR input to the serial channel
has changed states since the last time it was read by the CPU.
D Bit 2: MSR2 is the trailing edge of ring indicator (TERI) bit. TERI indicates that the RIx input to the serial
channel has changed states from low to high since the last time it was read by the CPU. High-to-low
transitions on RI do not activate TERI.
D Bit 3: MSR3 is the delta data carrier detect (∆ DCD) bit. ∆ DCD indicates that the DCD input to the serial
channel has changed states since the last time it was read by the CPU.
D Bit 4: MSR4 is the clear-to-send (CTS) bit. CTS is the complement of the CTS input from the modem
indicating to the serial channel that the modem is ready to receive data from SOUT. When the serial channel
is in the loop mode (MCR4 = 1), MSR4 reflects the value of RTS in the MCR.
D Bit 5: MSR5 is the data set ready DSR bit. DSR is the complement of the DSR input from the modem to
the serial channel that indicates that the modem is ready to provide received data from the serial channel
receiver circuitry. When the channel is in the loop mode (MCR4 is set), MSR5 reflects the value of DTR in
the MCR.
D Bit 6: MSR6 is the ring indicator (RI) bit. RI is the complement of the RIx inputs. When the channel is in the
loop mode (MCR4 is set), MSR6 reflects the value of OUT1 in the MCR.
D Bit 7: MSR7 is the data carrier detect (DCD) bit. Data carrier detect indicates the status of the data carrier
detect (DCD) input. When the channel is in the loop mode (MCR4 is set), MSR7 reflects the value of OUT2
in the MCR.
Reading the MSR clears the delta modem status indicators but has no affect on the other status bits. For LSR
and MSR, the setting of status bits is inhibited during status register read operations. If a status condition is
generated during a read IOR operation, the status bit is not set until the trailing edge of the read. When a status
bit is set during a read operation and the same status condition occurs, that status bit is cleared at the trailing
edge of the read instead of being set again. In the loopback mode when modem status interrupts are enabled,
CTS, DSR, RI, and DCD inputs are ignored; however, a modem status interrupt can still be generated by writing
to MCR3 – MCR0. Applications software should not write to the MSR.
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