TL16C554 Datasheet, PDF (22/33 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENT

TL16C554, TL16C554I
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS165D – JANUARY 1994 – REVISED JULY 1998
PRINCIPLES OF OPERATION
line status register (LSR) (continued)
D Bit 4: LSR4 is the break interrupt (BI) bit. Break interrupt is set when the received data input is held in the
spacing (low) state for longer than a full word transmission time (start bit + data bits + parity + stop bits).
The BI indicator is cleared when the CPU reads the contents of the LSR. In the FIFO mode, this is associated
with a particular character in the FIFO. LSR2 reflects the BI when the break character is at the top of the
FIFO. The error is detected by the CPU when its associated character is at the top of the FIFO during the
first LSR read. Only one zero character is loaded into the FIFO when BI occurs.
LSR1 – LSR4 are the error conditions that produce a receiver line status interrupt (priority 1 interrupt in the
interrupt identification register) when any of the conditions are detected. This interrupt is enabled by setting IER2
in the interrupt enable register.
D Bit 5: LSR5 is the transmitter holding register empty (THRE) bit. THRE indicates that the ACE is ready to
accept a new character for transmission. The THRE bit is set when a character is transferred from the
transmitter holding register (THR) into the transmitter shift register (TSR). LSR5 is cleared by the loading
of the THR by the CPU. LSR5 is not cleared by a CPU read of the LSR. In the FIFO mode, when the transmit
FIFO is empty, this bit is set. It is cleared when one byte is written to the transmit FIFO. When the THRE
interrupt is enabled by IER1, THRE causes a priority 3 interrupt in the IIR. If THRE is the interrupt source
indicated in IIR, INTRPT is cleared by a read of the IIR.
D Bit 6: LSR6 is the transmitter register empty (TEMT) bit. TEMT is set when the THR and the TSR are both
empty. LSR6 is cleared when a character is loaded into THR and remains low until the character is
transferred out of TXx. TEMT is not cleared by a CPU read of the LSR. In the FIFO mode, when both the
transmitter FIFO and shift register are empty, this bit is set.
D Bit 7: LSR7 is the receiver FIFO error bit. The LSR7 bit is cleared in the TL16C450 mode (see FCR bit 0).
In the FIFO mode, it is set when at least one of the following data errors is in the FIFO: parity error, framing
error, or break interrupt indicator. It is cleared when the CPU reads the LSR if there are no subsequent errors
in the FIFO.
NOTE
The LSR may be written. However, this function is intended only for factory test. It should be considered as read
only by applications software.
Table 6. Line Status Register BIts
LSR BITS
LSR0 data ready (DR)
LSR1 overrun error (OE)
LSR2 parity error (PE)
LSR3 framing error (FE)
LSR4 break interrupt (BI)
LSR5 transmitter holding register empty (THRE)
LSR6 transmitter register empty (TEMT)
LSR7 receiver FIFO error
1
Ready
Error
Error
Error
Break
Empty
Empty
Error in FIFO
0
Not ready
No error
No error
No error
No break
Not empty
Not empty
No error in FIFO
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