TL16C554 Datasheet, PDF (16/33 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENT

TL16C554, TL16C554I
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS165D – JANUARY 1994 – REVISED JULY 1998
PRINCIPLES OF OPERATION
accessible registers
The system programmer, using the CPU, has access to and control over any of the ACE registers that are
summarized in Table 1. These registers control ACE operations, receive data, and transmit data. Descriptions
of these registers follow Table 3.
Table 3. Summary of Accessible Registers
ADDRESS
REGISTER
MNEMONIC
0
RBR
(read only)
0
THR
(write only)
0†
DLL
1†
DLM
1
IER
BIT 7
Data Bit 7
(MSB)
Data BIt 7
Bit 7
Bit 15
0
BIT 6
Data Bit 6
Data BIt 6
Bit 6
Bit 14
0
2
FCR
Receiver Receiver
(write only) Trigger
Trigger
(MSB)
(LSB)
2
IIR
FIFOs
FIFOs
(read only) Enabled‡ Enabled‡
3
LCR
(DLAB)
Set break
Divisor
latch
access bit
4
MCR
0
0
5
LSR
Error in
(TEMT)
receiver
FIFO‡
Transmitter
registers
empty
6
MSR
(DCD)
(RI)
Data
Ring
carrier
indicator
detect
7
SCR
Bit 7
Bit 6
† _{DLAB = 1}
‡ _{These bits are always 0 when FIFOs are disabled.}
BIT 5
Data Bit 5
Data BIt 5
Bit 5
Bit 13
0
Reserved
0
Stick parity
0
(THRE)
Transmitter
holding
register
empty
(DSR)
Data set
ready
Bit 5
REGISTER ADDRESS
BIT 4
BIT 3
BIT 2
Data
Bit 4
Data Bit 3 Data Bit 2
Data
BIt 4
Data BIt 3 Data BIt 2
Bit 4
Bit 3
Bit 2
Bit 12
Bit 11
Bit 10
0
(EDSSI) (ERLSI)
Enable
Enable
modem receiver
status line status
interrupt interrupt
Reserved
0
(EPS)
Even
parity
select
Loop
(BI)
Break
interrupt
DMA
mode
select
Interrupt
ID Bit (3)‡
(PEN)
Parity
enable
OUT2
Enable
external
interrupt
(INT)
(FE)
Framing
error
Transmit
FIFO reset
Interrupt ID
Bit (2)
(STB)
Number of
stop bits
Reserved
(PE)
Parity error
(CTS)
Clear to
send
Bit 4
(∆ DCD)
Delta data
carrier
detect
Bit 3
(TERI)
Trailing
edge ring
indicator
Bit 2
BIT 1
Data Bit 1
Data BIt 1
Bit 1
Bit 9
(ETBEI)
Enable
transmitter
holding
register
empty
interrupt
Receiver
FIFO reset
Interrupt ID
Bit (1)
(WLSB1)
Word length
select bit 1
(RTS)
Request to
send
(OE)
Overrun
error
(∆ DSR)
Delta data
set ready
Bit 1
BIT 0
Data Bit 0
(LSB)
Data BIt 0
Bit 0
Bit 8
(ERBI)
Enable
received
data
available
interrupt
FIFO Enable
0 If interrupt
pending
(WLSB0)
Word length
select bit 0
(DTR) Data
terminal
ready
(DR)
Data ready
(∆ CTS)
Delta
clear to send
Bit 0
16
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