TL16C554 Datasheet, PDF (23/33 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENT

TL16C554, TL16C554I
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS165D – JANUARY 1994 – REVISED JULY 1998
PRINCIPLES OF OPERATION
modem control register (MCR)
The MCR controls the interface with the modem or data set as described in Figure 16. MCR can be written and
read. The RTS and DTR outputs are directly controlled by their control bits in this register. A high input asserts
a low signal (active) at the output terminals. MCR bits 0, 1, 2, 3, and 4 are shown as follows:
D Bit 0: When MCR0 is set, the DTR output is forced low. When MCR0 is cleared, the DTR output is forced
high. The DTR output of the serial channel may be input into an inverting line driver in order to obtain the
proper polarity input at the modem or data set.
D Bit1: When MCR1 is set, the RTS output is forced low. When MCR1 is cleared, the RTS output is forced
high. The RTS output of the serial channel may be input into an inverting line driver to obtain the proper
polarity input at the modem or data set.
D Bit 2: MCR2 has no affect on operation.
D Bit 3: When MCR3 is set, the external serial channel interrupt is enabled.
D Bit 4: MCR4 provides a local loopback feature for diagnostic testing of the channel. When MCR4 is set,
serial output TXx is set to the marking (high) state and SIN is disconnected. The output of the TSR is looped
back into the RSR input. The four modem control inputs (CTS, DSR, DCD, and RI) are disconnected. The
modem control outputs (DTR and RTS) are internally connected to the four modem control inputs. The
modem control output terminals are forced to their inactive (high) state on the TL16C554. In the diagnostic
mode, data transmitted is immediately received. This allows the processor to verify the transmit and receive
data paths of the selected serial channel. Interrupt control is fully operational; however, interrupts are
generated by controlling the lower four MCR bits internally. Interrupts are not generated by activity on the
external terminals represented by those four bits.
D Bit 5 – Bit 7: MCR5, MCR6, and MCR7 are permanently cleared.
MODEM CONTROL REGISTER
MCR MCR MCR MCR MCR MCR MCR MCR
76
5
43
21
0
Data Terminal
Ready
Request
to Send
0 = DTR Output Inactive (high)
1 = DTR Output Active (low)
0 = RTS Output Inactive (high)
1 = RTS Output Active (low)
Out1 (internal) No affect on external operation
Out2 (internal) 0 = External Interrupt Disabled
1 = External Interrupt Enabled
Loop
0 = Loop Disabled
1 = Loop Enabled
Bits Are Set to Logic 0
Figure 16. Modem Control Register Contents
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
23