TL16C554 Datasheet, PDF (4/33 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENT

TL16C554, TL16C554I
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS165D – JANUARY 1994 – REVISED JULY 1998
functional block diagram^†
D7 – D0
Data
Bus
8
TL16C550B
Circuitry
Receive
Control _RXx
Logic
A2 – A0
CSx
IOR, IOW
RESET
Control
Logic
INTx Interrupt
TXRDY, RXRDY ^Logic
TL16C550B
Circuitry
TL16C550B
Circuitry
XTAL1 Clock
XTAL2 Circuit
TL16C550B
Circuitry
† _{For TL16C550 circuitry, refer to the TL16C550B data sheet.}
Transmit
Control TXx
Logic
Modem
Control
Logic
CTSx
RTSx
DSRx
DTRx
RIx
DCDx
Terminal Functions
TERMINAL
NAME
FN
NO.
PN ^I/O
NO.
DESCRIPTION
A0
34
48
I Register select terminals. A0, A1, and A2 are three inputs used during read and write operations to
A1
33
47
select the ACE register to read or write.
A2
32
46
CSA, CSB,
CSC, CSD
16, 20, 28, 33, I Chip select. Each chip select (CSx) enables read and write operations to its respective channel.
50, 54 68, 73
CTSA, CTSB, 11, 25, 23, 38, I Clear to send. CTSx is a modem status signal. Its condition can be checked by reading bit 4 (CTS)
CTSC, CTSD 45, 59 63, 78
of the modem status register. CTS has no affect on the transmit or receive operation.
D7 – D0
66 – 68 15–11, I/O Data bus. Eight data lines with 3-state outputs provide a bidirectional path for data, control, and status
1 – 5 9–7
information between the TL16C554 and the CPU. D0 is the least significant bit (LSB).
DCDA, DCDB, 9, 27, 19,42, I Data carrier detect. A low on DCDx indicates the carrier has been detected by the modem. The
DCDC, DCDD 43, 61 59, 2
condition of this signal is checked by reading bit 7 of the modem status register.
DSRA, DSRB,
DSRC, DSRD
10, 26, 22, 39,
44, 60 62, 79
I
Data set ready. DSRx is a modem status signal. Its condition can be checked by reading bit 5 (DSR)
of the modem status register. DSR has no affect on the transmit or receive operation.
DTRA, DTRB,
DTRC, DTRD
12, 24, 24, 37, O
46, 58 64, 77
Data terminal ready. DTRx is an output that indicates to a modem or data set that the ACE is ready
to establish communications. It is placed in the active state by setting the DTR bit of the modem
control register. DTRx is placed in the inactive state (high) either as a result of the master reset during
loop mode operation or clearing bit 0 (DTR) of the modem control register.
GND
6, 23, 16, 36,
40, 57 56, 76
Signal and power ground
INTN
65
6
I Interrupt normal. INTN operates in conjunction with bit 3 of the modem status register and affects
operation of the interrupts (INTA, INTB, INTC, and INTD) for the four universal asynchronous
receiver/transceivers (UARTs) per the following table.
INTN
OPERATION OF INTERRUPTS
Brought low or Interrupts are enabled according to the state of OUT2 (MCR bit 3). When the MCR
allowed to float bit 3 is cleared, the 3-state interrupt output of that UART is in the high-impedance
state. When the MCR bit 3 is set, the interrupt output of the UART is enabled.
Brought high Interrupts are always enabled, overriding the OUT2 enables.
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