TL16C554 Datasheet, PDF (14/33 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENT

TL16C554, TL16C554I
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS165D – JANUARY 1994 – REVISED JULY 1998
PARAMETER MEASUREMENT INFORMATION
IOR
(RD RBR)
SIN
(first byte that reaches
the trigger level)
Sample
Clock
Stop
50%
Active
(see Note A)
td9
(see Note B)
RXRDY
50%
50%
tpd5
NOTES: A. This is the reading of the last byte in the FIFO.
B. If FCR0 = 1, td9 = 3 RCLK cycles. For a trigger change level interrupt, td9 = 8 RCLK.
Figure 13. Receiver Ready Mode 1 Timing Waveforms
IOW
(WR MCR)
RTSx, DTRx
CTSx, DSRx,
DCDx
INTx
IOR
(RD MSR)
RIx
50%
tpd6
50%
50%
50%
tpd6
tpd7
50%
50%
tpd8
50%
tpd7
50%
50%
50%
tpd9
50%
50%
Figure 14. Modem Control Timing Waveforms
14
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