TL16C554 Datasheet, PDF (21/33 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENT

TL16C554, TL16C554I
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS165D – JANUARY 1994 – REVISED JULY 1998
PRINCIPLES OF OPERATION
line control register (LCR) (continued)
LCR
7
LINE CONTROL REGISTER
LCR LCR LCR LCR LCR LCR
65
4
3
21
LCR
0
Word Length
Select
0 0 = 5 Data Bits
0 1 = 6 Data Bits
1 0 = 7 Data Bits
1 1 = 8 Data bits
Stop Bit
Select
0 = 1 Stop Bit
1 = 1.5 Stop Bits if 5 Data Bits Selected
2 Stop Bits if 6, 7, 8 Data Bits Selected
Parity Enable
0 = Parity Disabled
1 = Parity Enabled
Even Parity
Select
0 = Odd Parity
1 = Even Parity
Stick Parity
0 = Stick Parity Disabled
1 = Stick Parity Enabled
Break Control
0 = Break Disabled
1 = Break Enabled
Divisor Latch 0 = Access Receiver Buffer
Access BIt 1 = Access Divisor Latches
Figure 15. Line Control Register Contents
line status register (LSR)
The LSR is a single register that provides status indicators. The LSR shown in Table 6 is described in the
following bulleted list:
D Bit 0: LSR0 is the data ready (DR) bit. Data ready is set when an incoming character is received and
transferred into the receiver buffer register or the FIFO. LSR0 is cleared by a CPU read of the data in the
receiver buffer register or the FIFO.
D Bit 1: LSR1 is the overrun error (OE) bit. An overrun error indicates that data in the receiver buffer register
is not read by the CPU before the next character is transferred into the receiver buffer register overwriting
the previous character. The OE indicator is cleared whenever the CPU reads the contents of the LSR. An
overrun error occurs in the FIFO mode after the FIFO is full and the next character is completely received.
The overrun error is detected by the CPU on the first LSR read after it happens. The character in the shift
register is not transferred to the FIFO, but it is overwritten.
D Bit 2: LSR2 is the parity error (PE) bit. A parity error indicates that the received data character does not
have the correct parity as selected by LCR3 and LCR4. The PE bit is set upon detection of a parity error
and is cleared when the CPU reads the contents of the LSR. In the FIFO mode, the parity error is associated
with a particular character in the FIFO. LSR2 reflects the error when the character is at the top of the FIFO.
D Bit 3: LSR3 is the framing error (FE) bit. A framing error indicates that the received character does not have
a valid stop bit. LSR3 is set when the stop bit following the last data bit or parity bit is detected as a zero
bit (spacing level). The FE indicator is cleared when the CPU reads the contents of the LSR. In the FIFO
mode, the framing error is associated with a particular character in the FIFO. LSR3 reflects the error when
the character is at the top of the FIFO.
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