TL16C554 Datasheet, PDF (18/33 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENT

TL16C554, TL16C554I
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS165D – JANUARY 1994 – REVISED JULY 1998
PRINCIPLES OF OPERATION
FIFO interrupt mode operation (continued)
1. When the following conditions exist, a FIFO character time-out interrupt occurs:
a. Minimum of one character in FIFO
b. Last received serial character is longer than four continuous previous character times ago. (If two stop
bits are programmed, the second one is included in the time delay.)
c. The last CPU of the FIFO read is more than four continuous character times earlier. At 300 baud and
12-bit characters, the FIFO time-out interrupt causes a latency of 160 ms maximum from received
character to interrupt issued.
2. By using the XTAL1 input for a clock signal, the character times can be calculated. The delay is proportional
to the baud rate.
3. The time-out timer is reset after the CPU reads the receiver FIFO or after a new character is received. This
occurs when there has been no time-out interrupt.
4. A time-out interrupt is cleared and the timer is reset when the CPU reads a character from the receiver FIFO.
Transmit interrupts occurs as follows when the transmitter and transmit FIFO interrupts are enabled
(FCR0 = 1, IER = 1).
1. When the transmitter FIFO is empty, the transmitter holding register interrupt (IIR = 02) occurs. The interrupt
is cleared when the transmitter holding register is written to or the IIR is read. One to sixteen characters can
be written to the transmit FIFO when servicing this interrupt.
2. The transmitter FIFO empty indicators are delayed one character time minus the last stop bit time whenever
the following occurs:
THRE = 1, and there has not been a minimum of two bytes at the same time in transmit FIFO since the last
THRE = 1. The first transmitter interrupt after changing FCR0 is immediate, however, assuming it is
enabled.
Receiver FIFO trigger level and character time-out interrupts have the same priority as the receive data
available interrupt. The transmitter holding register empty interrupt has the same priority as the transmitter FIFO
empty interrupt.
FIFO polled mode operation
Clearing IER0, IER1, IER2, IER3, or all to zero with FCR0 = 1 puts the ACE into the FIFO polled mode. receiver
and transmitter are controlled separately. Either or both can be in the polled mode.
In the FIFO polled mode, there is no time-out condition indicated or trigger level reached. However, the Receiver
and transmit FIFOs still have the capability of holding characters. The LSR must be read to determine the ACE
status.
interrupt enable register (IER)
The IER independently enables the four serial channel interrupt sources that activate the interrupt (INTA, B, C,
D) output. All interrupts are disabled by clearing IER0 – IER3 of the IER. Interrupts are enabled by setting the
appropriate bits of the IER. Disabling the interrupt system inhibits the IIR and the active (high) interrupt output.
All other system functions operate in their normal manner, including the setting of the LSR and MSR. The
contents of the IER are shown in Table 3 and described in the following bulleted list:
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