5962-1123701VXC Datasheet, PDF (8/25 Pages) Texas Instruments – 16-Mb RADIATION-HARDENED SRAM

SMV512K32-SP
SLVSA21H – JUNE 2011 – REVISED JULY 2013
Table 4. AC Characteristics Read Cycle ⁽¹⁾ (continued)
SYMBOL
PARAMETER
t_GLMV
t_GLMX
t_ETMX
t_ETMV
t_GHMZ ⁽³⁾
t_EFMZ ⁽³⁾
GZ-controlled error flag valid
GZ-controlled error flag enable time
E-controlled error flag enable time
E-controlled error flag time
GZ-controlled error flag tri-state time
Chip enable change to MBE tri-state
(3) Parameters ensured by design and/or characterization if not production tested.
MIN
3.5
3.5
3.5
3.5
MAX
8.6
20
5
5
UNIT
ns
ns
ns
ns
ns
ns
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FIGURE
Figure 6
Figure 6
Figure 5
Figure 5
Figure 6
Figure 5
A(18:0)
t_AVAV1
DQ(31:0) ^{Previous valid data}
Valid data
MBE
t_AXQX, t_AXMX
t_AVQV1, t_AVMV
Valid data
Assumptions: E1Z low, E2 high, WZ high, GZ low and SCRUBZ high. Reading uninitialized addresses will
cause MBE to be asserted.
Figure 4. SRAM Read Cycle 1, Address-Controlled Access
A(18:0)
Latter of E1Z
low of E2 high
DQ(31:0)
MBE
t_ETQX, t_ETMX
t_ETQV, t_ETMV
t_EFQZ
Data valid
t_EFMZ
Data valid
Assumptions: GZ low, WZ high and SCRUBZ high. Reading uninitialized addresses will cause
MBE to be asserted.
Figure 5. Read Cycle 2, Chip Enable-Controlled Access
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