5962-1123701VXC Datasheet, PDF (6/25 Pages) Texas Instruments – 16-Mb RADIATION-HARDENED SRAM

SMV512K32-SP
SLVSA21H – JUNE 2011 – REVISED JULY 2013
OPERATIONS
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SMV512K32 has four control inputs called chip enable-1 (E1Z), chip enable-2 (E2), write enable (WZ) and output
enable (GZ); 19 address inputs A[18:0] and a 32-bit bidirectional data bus DQ[31:0]. E1Z and E2 enable control
device selection, active and stand-by modes (with and without scrub). WZ controls read and write operations.
During read operation, GZ must be asserted to enable the outputs.
Table 2. SRAM Device Control Operation Truth Table
E1Z
E2
GZ
WZ
MBE
I/O MODE
MODE
H
X
X
X
X
DQ[31:0] 3-State
Standby without EDAC scrub
enable
L
L
X
X
X
DQ[31:0] 3-state
Standby with EDAC scrub
enable ⁽¹⁾
L
H
L
H
X
DQ[31:0] Data out
Word read
L
H
X
L
X
DQ[31:0] Data in
Word write
L
H
H
H
L
DQ[31:0] 3-state
3-state
L
H
H
H
H
DQ[31:0] Data in/out
EDAC function select
(see Table 7)⁽²⁾
(1) During SCRUB mode, MBE is 3-state if GZ is high and indicates multiple or single bit error if GZ is low.
(2) Special precautions must be observed to prevent accidental over-writing of the Control Register in the memory after a bit error is
detected and the memory drives MBE high (please refer to the next section).
Procedures for Controlling the MBE Pin
A 1-kΩ resistor must be attached from the MBE pin to ground to insure that MBE cannot float high during time
intervals when it is not actively driven HIGH by the memory or actively driven by the external memory control.
During normal EDAC operation, the control registers are set as shown by Sequence 1 in Table 3. Whenever the
EDAC circuit encounters either a multiple-bit error or single-bit error (depending on user configuration), the MBE
pin is driven high by the memory as shown by Sequence 2 in Table 3 . Following this the MBE will need to be
reset (low) to restore the detection circuit for the next bit error event. The MBE pin will be pulled low by the 1-kΩ
resistor when GZ is switched to high state. However, to accomplish the MBE reset properly and avoid an
accidental write to the control register, the memory must first be disabled by switching either E1Z to high or E2 to
low (Sequence 3) before switching GZ from low to high (Sequence 4). Note however, that if E1Z is switched to
high this will disable scrub during the interval that GZ is being set high after the memory is disabled.
The memory must remain disabled long enough to insure that MBE is pulled low before the memory is enabled
again. During the time the memory is disabled the address at which the MBU was detected must also be
changed to access the last known error free address. After the address is changed the memory can be enabled
with GZ high. Then an Output Enable-controlled read operation can be performed using the last known error free
address. This turns off the MBE error flag in the memory and causes the memory to drive MBE low after the GZ-
controlled output data valid time, t_GLMV.
This procedure resets the memory back into its normal EDAC read state in which the memory will drive MBE low
sequentially for each read operation until the next bit error is encountered. This avoids accidental over-writing of
the Control Register in the memory. After this procedure is completed the system protocol for responding to bit
errors can be executed.
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