5962-1123701VXC Datasheet, PDF (5/25 Pages) Texas Instruments – 16-Mb RADIATION-HARDENED SRAM

SMV512K32-SP
www.ti.com
SLVSA21H – JUNE 2011 – REVISED JULY 2013
ELECTRICAL CHARACTERISTICS
T_C = -55°C to 125°C, V_DD1 = 1.7 V to 1.9 V, V_DD2 = 3 V to 3.6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
V_IH
HIgh-level input voltage
V_IL
Low-level input voltage
V_OL
Low-level output voltage
I_OL = 4 mA, V_DD2 = V_DD2(min)
V_OH
C_IN ⁽¹⁾
C_IO ⁽¹⁾
I_IN
I_OZ
I_OS ^{(2) (3)}
High-level output voltage
Input capacitance
Bidirectional I/O capacitance
Input leakage current
Tri-state output leakage
current
Short-circuit output current
I_DD1(OP₁)
V_DD1 supply operating current
at 1 MHz
I_DD1(OP₂)
V_DD1 supply operating current
at 50 MHz
I_DD2(OP₁)
V_DD2 supply operating current
at 1 MHz
I_DD2(OP₂)
V_DD2 supply operating current
at 50 MHz
I_DD1(SB) ⁽⁴⁾
Supply stand-by current
at 0 MHz
I_DD2(SB) ⁽⁴⁾
Supply stand-by current
at 0 MHz
I_DD1(SB) ⁽⁴⁾
Supply stand-by current
A[16:0] at 50 MHz
I_DD2(SB) ⁽⁴⁾
Supply stand-by current
A[16:0] at 50 MHz
I_OH = -4 mA, V_DD2 = V_DD2(min)
f = 1 MHz at 0 V
f = 1 MHz at 0 V
V_IN=V_DD2 and V_SS
V_O= V_DD2 and V_SS
V_DD2 = V_DD2(max), GZ=V_DD2(max)
V_DD2 = V_DD2(max), V_O = V_DD2
V_DD = V_DD2(max), V_O = V_SS
Input: V_IL = V_SS + 0.2 V,
V_IH = V_DD2 - 0.2 V, I_OUT = 0 A,
V_DD1 = V_DD1(max),
V_DD2 = V_DD2(max)
Write
Read
–55°C to 25°C
125°C
–55°C to 25°C
125°C
Input: V_IL = V_SS + 0.2 V,
V_IH = V_DD2 - 0.2 V, I_OUT = 0 A,
V_DD1 = V_DD1(max),
V_DD2 = V_DD2(max)
Write
Read
–55°C to 25°C
125°C
–55°C to 25°C
125°C
Input: V_IL = V_SS + 0.2 V,
V_IH = V_DD2 - 0.2 V, I_OUT = 0 A,
V_DD1 = V_DD1(max),
V_DD2 = V_DD2(max)
Write
Read
–55°C to 25°C
125°C
–55°C to 25°C
125°C
Input: V_IL = V_SS + 0.2 V,
V_IH = V_DD2 - 0.2 V, I_OUT = 0 A,
V_DD1 = V_DD1(max),
V_DD2 = V_DD2(max)
Write
Read
–55°C to 25°C
125°C
–55°C to 25°C
125°C
CMOS inputs, I_OUT = 0 A
E1Z = V_DD2 - 0.2 V, E2 = GND,
V_DD1 = V_DD1(max),
V_DD2 = V_DD2(max)
CMOS inputs, I_OUT = 0 A
E1Z = V_DD2 - 0.2 V, E2 = GND,
V_DD1 = V_DD1(max),
V_DD2 = V_DD2(max)
CMOS inputs, I_OUT = 0 A
E1Z = V_DD2 - 0.2 V, E2 = GND,
V_DD1 = V_DD1(max),
V_DD2 = V_DD2(max)
CMOS inputs, I_OUT = 0 A
E1Z = V_DD2 - 0.2 V, E2 = GND,
V_DD1 = V_DD1(max),
V_DD2 = V_DD2(max)
–55°C to 25°C
125°C
–55°C to 25°C
125°C
–55°C to 25°C
125°C
–55°C to 25°C
125°C
MIN
0.7 x
V_DD2
0.8 x
V_DD2
–500
–500
MAX
0.3 x
V_DD2
0.2 x
V_DD2
4.5
4.5
500
500
UNIT
V
V
V
V
pF
pF
nA
nA
–46
46 mA
18
31
mA
13
27
635
460
mA
365
315
255
µA
255
5.2
mA
5.1
5.9
1.2
mA
275
120
0.375
mA
17
330
µA
330
4.4
mA
21
1.6
mA
0.8
(1) Measured for initial qualification and after process or design changes that could affect input/output capacitance.
(2) Provided as a design limit but not guaranteed or tested.
(3) No more than one output may be shorted at a time for maximum duration of one second.
(4) V_IH = V_DD2(max), V_IL = 0 V
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