5962-1123701VXC Datasheet, PDF (13/25 Pages) Texas Instruments – 16-Mb RADIATION-HARDENED SRAM

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SMV512K32-SP
SLVSA21H – JUNE 2011 – REVISED JULY 2013
A[18:0]
E1Z
t_AVET
t_AVAV
t_ETEF
t_EFAX
E2
or
E1Z
E2
WZ
DQ[31:0]
MBE
t_ETWH2
t_WHEF
t_WHDX
Applied Din
t_DVWH
t_WHQX
t_WHMX
t_WHQV
t_WHMV
t_EFQZ
Valid
t_EFMZ
Valid
Assumptions: Either E1Z,/E2 scenario can occur, SCRUBZ high, GZ low
Figure 10. SRAM Write Cycle 3, Enable Controlled Write With Data Write Through Controlled by WZ
A[18:0]
E1Z
t_AVET
t_AVAV2
t_ETEF1
E2
or
E1Z
E2
WZ
DQ[31:0]
t_ETWH2
t_WHEF1
t_WHAX1
t_WHDX
Applied Din
t_DVWH
Assumptions: Either E1Z,/E2 scenario can occur, SCRUBZ high, GZ High
Figure 11. SRAM Write Cycle 3a, Enable Controlled Write Only With GZ Fixed High
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