5962-1123701VXC Datasheet, PDF (7/25 Pages) Texas Instruments – 16-Mb RADIATION-HARDENED SRAM

SMV512K32-SP
www.ti.com
SLVSA21H – JUNE 2011 – REVISED JULY 2013
Table 3. Example Control Settings for Resetting MBE
SEQUENCE E1Z E2 GZ WZ MBE
I/O MODE
1
LHLH
L DQ[31:0] Data out
2
LHLH
H DQ[31:0] Data out
3
H
L
L
H
H DQ[31:0] Data out
4
H L H H H → L DQ[31:0] Tri-state
5
L HHH
L DQ[31:0] Tri-state
6
LHLH
L DQ[31:0] Data out
MODE
Normal read mode with EDAC enabled
MBE driven high when single bit or multiple bit error
(depending on user configuration) is detected during read
Memory disabled
Outputs tri-stated and MBE pulled low by load R
Read at a last known error free address⁽¹⁾
Output enable-controlled read⁽²⁾
(1) During this operation MBE drive circuitry in the memory is tri-stated but MBE is held low by the 1-kΩ resistor to ground.
(2) During this operation MBE is actively driven low by the MBE drive circuitry in the memory after a time, t_GLMV, and the memory is back to
the original state corresponding to normal read mode with EDAC enabled.
Read Operations
A combination of E1Z low, E2 high and WZ high defines a read cycle. GZ low enables the outputs to drive read
data to the DQ pins. Read access time is measured from the latter of device enable, output enable or valid
address to valid data output.
• SRAM read cycle 1 (Figure 4): Address controlled access is initiated by a change in address inputs while
device is selected with WZ high and GZ low. Valid data appears on DQ[31:0] after a specified t_AVQV is
satisfied. Outputs remain active throughout the entire cycle. As long as the device enable and output enable
are active, the minimum time between valid address changes is specified by the read cycle time t_AVAV.
• SRAM read cycle 2 (Figure 5): Chip-enable controlled access is initiated by the latter of either E1Z or E2
going active while GZ is low, WZ is high, and address remains stable for the entire cycle. After the specified
time t_ETQV, the 32-bit word addressed by A[18:0] is accessed and appears at DQ[31:0].
• SRAM read cycle 3 (Figure 6): Output-enable controlled access is initiated by GZ going active while E1Z and
E2 are asserted, WZ is de-asserted, and address is stable. Read access time is t_GLQV unless t_AVQV or t_ETQV
have not been satisfied.
If EDAC is turned on during read operation:
• If MBE is low, data is valid.
• If MBE is high, data is corrupted (dependent on EDAC programming configuration on A[12], MBE can
indicate a single bit or double bit error). Single bit error is correctable by EDAC.
Table 4. AC Characteristics Read Cycle ⁽¹⁾
SYMBOL
t_AVAV1
t_AVQV1
t_AXQX
t_GLQX1
t_GLQV
t_GHQZ1
t_ETQX
t_ETQV
t_EFQZ
t_AVMV
t_AXMX
PARAMETER
Read cycle time
Address to data valid from address change⁽²⁾
Output hold time
GZ-controlled output enable time
GZ-controlled output data valid
GZ-controlled output enable tri-state time
E-controlled output enable time
E-controlled access time
E-controlled tri-state time
Address to error flag valid
Address to error flag hold time from address change
MIN
20
7.5
3.5
3.5
3.5
3.5
7.5
(1) T_C = -55°C to 125°C, V_DD1 = 1.7 V to 1.9 V, V_DD2 = 3 V to 3.6 V (unless otherwise noted).
(2) 20 ns at 5-pF load.
MAX
20
8.6
5
20
5
20
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
FIGURE
Figure 4
Figure 4
Figure 4
Figure 6
Figure 6
Figure 6
Figure 5
Figure 5
Figure 5
Figure 4
Figure 4
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