5962-1123701VXC Datasheet, PDF (15/25 Pages) Texas Instruments – 16-Mb RADIATION-HARDENED SRAM

SMV512K32-SP
www.ti.com
SLVSA21H – JUNE 2011 – REVISED JULY 2013
MBE (OUTPUT)
H
L
X
X
X
Table 6. EDAC Control Operation Mode Truth Table
SCRUBZ
H
H
H
H
L
BUSYZ
H
H
H
L
X
Read
Read
X
I/O MODE
X
Not accessible
MODE
Data error detected⁽¹⁾
Valid data out⁽¹⁾
Device ready
Device ready/early scrub request
coming
Device busy (scrub in progress)
(1) MBE is only valid in EDAC operation modes (Read with EDAC enable or scrub).
MBE indicates Multiple Bit Error if A[12] bit in the control register is ‘0’.
MBE indicates Single Bit Error if A[12] bit in the control register is ‘1’.
To allow system design flexibility, the time delay between falling edges of BUSYZ and SCRUBZ as well as the
scrub rate are user programmable (see the control register programming description below). Depending on
environment and usage, some users may want a high scrub rate to minimize error rate at the sacrifice of reduced
data throughput, while others may want a lower scrub rate to increase the throughput and accept a higher error
rate.
Data errors are detected and corrected not only during scrub cycles, but also during normal read cycles.
EDAC Configuration and Scrub Address Polling (Master Device Only)
The user can program the scrub rate and the edge relationship between BUSYZ and SCRUBZ by writing
configuration data to the control register. The value recorded in the control register determines scrub rate,
SCRUBZ to BUSYZ delay, EDAC bypass selection, scrub enable/disable and single bit or multiple bit error
detection. See Table 8 for more detail.
Table 9 and Table 10 give typical timing characteristics for various configuration options. Table 11 gives the AC
characteristics for EDAC functions.
The following EDAC control operations are defined by Table 7.
• Control register write (Figure 15): This mode is used to write configuration values to the EDAC control
register.
• Control register read (Figure 16): This mode is used to read the contents of the EDAC control register.
• Scrub address counter read (Figure 17): This mode is to read out the address counter which is used as a
pointer for scrub operations. The address counter is reset to all ‘1’ when the configuration register is written. It
is then automatically incremented for each scrub cycle. In the event of a single or multiple bit error detected
during a scrub cycle, the address can be polled to determine the location of the data error. During the
address counter read, the 19 bits of the counter are output on data bits DQ[18:0]. The value of the other data
bits DQ[31:19] are ignored.
Table 7. EDAC Function Select Truth Table⁽¹⁾
E1Z
E2
GZ
WZ
MBE
A7
A8
A9
A10
L
H
H
H
H
X
X
L
L
L
H
H
H
H
X
X
H
L
L
H
H
H
H
H
X
X
H
(1) All other combinations of A7-A10 are reserved and should be avoided.
MODE
Write control register
Read control register
Address counter read
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