5962-1123701VXC Datasheet, PDF (14/25 Pages) Texas Instruments – 16-Mb RADIATION-HARDENED SRAM

SMV512K32-SP
SLVSA21H – JUNE 2011 – REVISED JULY 2013
www.ti.com
A[18:0]
E1Z
t_AVET
t_AVAV
t_ETEF
t_EFAX
E2
or
E1Z
E2
t_ETWH2
t_WHEF
WZ
GZ
DQ[31:0]
t_WHDX
t_DVWH
Applied Din
t_GLQV
t_EFQZ
Valid
t_GLQX
MBE
t_GLMX
Assumptions: Either E1Z,/E2 scenario can occur, SCRUBZ high
t_GLMV
t_EFMZ
Valid
Figure 12. SRAM Write Cycle 4, Enable Controlled Write With Data Write Through Controlled by GZ
Scrub Operation
The SMV512K32 uses embedded error detection and correction (EDAC) to correct single bit upset of each 32-bit
word. The device pins BUSYZ and SCRUBZ are used differently depending on whether the device is operated as
a slave device (MSS pin connected to VDD2) or as a master device (MSS pin connected to VSS2). The BUSYZ
pin is an output for the master device and is driven low to indicate that a scrub cycle is about to be initiated. The
BUSYZ signal can be used to generate wait states by the memory controller. The BUSYZ pin should should be
left unconnected for slave devices. The SCRUBZ pin is an output on the master device and an input on slave
devices. The master SCRUBZ pin is driven low when a scrub cycle initiates and can be used to trigger scrub
cycles for slave units by connecting their respective SCRUBZ pins to the SCRUBZ master output.
The EDAC operation truth table is shown in Table 6.
14
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