5962-1123701VXC Datasheet, PDF (16/25 Pages) Texas Instruments – 16-Mb RADIATION-HARDENED SRAM

SMV512K32-SP
SLVSA21H – JUNE 2011 – REVISED JULY 2013
www.ti.com
Table 8. EDAC Control Register Programming⁽¹⁾⁽²⁾
ADDRESS BIT
PARAMETER
VALUE
A[3:0]
Scrub rate – Rates are
approximate and will vary with
temperature and voltage
conditions as well as process
parameters
0–15
A[7:4]
A[8]
A[11]
A[12]
BUSYZ to SCRUBZ – Delays
are approximate and will vary
with temperature and voltage
conditions as well as process
parameters
0–15
EDAC bypass bit
0/1
Scrub enable bit
0/1
SE/DE indication bit
0/1
FUNCTION
As scrub rate changes from 0 to 15, then the interval between scrub cycles,
t_BLBL, will change as follows:
0 = N/A /xxxxxxxxxxx. 6 = 222 kHz xxx 11 = 7 kHz
1 = N/A /xxxxxxxxxxx. 7 = 111 kHz xxx 12 = 3.5 kHz
2 = N/A /xxxxxxxxxxx. 8 = 55 kHz xxxx. 13 = 1.75 kHz
3 = N/A .xxxxxxxxxx.x 9 = 28 kHz xxxx. 14 = 0.875 kHz
4 = 888 kHz xxxx xxx 10 = 14 kHz xxxx 15 = 0.433 kHz
5 = 444 kHz
See Table 9.
If A[7:4] changes from 0 to 15, the interval t_BLSL between falling edges of
BUSYZ and SCRUBZ will change as follows:
0 = 80 ns xxxxx 6 = 480 ns xxxxxx 11 = 820 ns
1 = 160 ns xxxx 7 = 560 ns xxxxxx 12 = 880 ns
2 = 220 ns xxxx 8 = 620 ns xxxxxx 13 = 960 ns
3 = 280 ns xxxx 9 = 680 ns xxxxxx 14 = 1020 ns
4 = 360 ns xxxx 10 = 760 ns xxxxx 15 = 1080 ns
5 = 420 ns
See Table 10.
0: Enable EDAC
1: Disable EDAC including scrub
0: Enable scrub
1: Disable scrub
0: MBE indicates multiple-bit error
1: MBE indicates single-bit error
(1) A(10:9) must be '00' during control register programming according to Table 7.
(2) A(18:13) are don't care.
xxx
NOTE
During power up, states of all registers are random so it is imperative that the user
execute Write Control Register and preferably Read Control Register to affirm desired
operations. The following values are recommended to set for initial use:
1. Scrub rate is 111 kHz.
2. t_BLSL is 760 ns.
3. EDAC bit is 0 (enabled).
4. Scrub enable bit is 0 (enabled).
5. SE/DE indication bit is 0 (multiple bit).
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