GC2011A Datasheet, PDF (6/50 Pages) Texas Instruments – 3.3V DIGITAL FILTER CHIP

GC2011A 3.3V DIGITAL FILTER CHIP
SLWS129A
1.2 GC2011A TO GC2011 COMPARISON
The GC2011A is designed to be a functional and footprint compatible replacement for the GC2011 chip. The
timing specifications for the GC2011A meet and exceed the timing specifications for the GC2011. Electrically the
GC2011A is a 3.3 volt only part, making it incompatible with the GC2011’s 5 volt mode. The GC2011A is fully compatible
with the GC2011’s 3.3 volt mode, but at a lower power consumption. See Section 7 for timing and electrical
specifications. NOTE: The GC2011A inputs are NOT 5 volt tolerant; chip damage may occur if the input voltages exceed
Vcc + 0.5V (3.8 volts). Designs using the GC2011 at 5 volts will need to add a 3.3 volt supply and voltage level
translators to use the GC2011A.
The function of the GC2011A has been slightly enhanced, but any enhancements are “backward” compatible
with the GC2011 so that a GC2011 user will not need to change any software or processing algorithms to use the
GC2011A chip. Highlights of the enhancements follow.
1.2.1 Offset Binary Conversion
Digital filter chips are commonly used with analog to digital converters (ADCs) or digital to analog converters
(DACs) which often require an offset binary data format rather than the two’s complement data format of the GC2011.
Offset binary data is easily converted to two’s compliment by inverting the most significant bit (MSB) of the data word.
The GC2011A has been enhanced to allow conversion between offset binary and two’s complement format by
optionally inverting the MSB of the input or output data. Four control bits (register address 12) have been added which,
when set high, invert the MSBs of the Ain, Bin Aout, and Bout data words. These control bits are cleared at power up
so that the GC2011A will power up in the GC2011’s two’s complement mode.
See Section 6.10 for details.
1.2.2 Clock Loss Detect and Power Down Modes
The GC2011 chip draws excessive current if operated without a clock signal. This is caused by internal
dynamic storage nodes being left in an unknown state when the clock is stopped. A clock loss detect circuit has been
added to the GC2011A that will put the chip in a fully static mode if the clock has stopped. The fully static mode powers
down the chip and reduces the power consumption down to a few microwatts until the clock resumes. The user can also
force the power down state if desired. Two control bits (register address 12) are used to control the clock loss detect
and power down modes. One control bit turns off the clock loss detect circuit, the other forces the power down mode.
Both bits are cleared at power up to keep GC2011 compatibility.
See Section 6.10 for details.
1.2.3 Control Interface
The control interface has been enhanced to use either the R/W and CS strobes of the original GC2011, or to
use the RE, WE and CE strobes used by most memory interfaces. If the RE pin is grounded, then the interface behaves
in the R/W and CS mode, where the WE pin becomes the R/W pin and the CE pin becomes the CS pin. The RE pin on
the GC2011A chip is a ground pin on the GC2011 chip, so that a GC2011A chip soldered into a GC2011 socket will
automatically operate in the GC2011 R/W and CS mode.
See Section 2.2 for details.
1.2.4 NEW_MODES Control Register
A control register at address 12 has been added to the GC2011A to control the new GC2011A modes. Address
12 was unused in the GC2011 chip so that existing GC2011 control software will not activate the new modes. This
control register powers up in the GC2011 compatible mode. See Section 6.10 for details.
Texas Instruments Incorporated
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This document contains information which may be changed at any time without notice