GC2011A Datasheet, PDF (13/50 Pages) Texas Instruments – 3.3V DIGITAL FILTER CHIP

GC2011A 3.3V DIGITAL FILTER CHIP
SLWS129A
symmetric filter modes. The feedback circuit will also negate the reverse data, if desired, to implement anti-symmetric
filters. In non-symmetric modes the feedback samples are cleared.
There are four filter coefficients stored within each filter cell. The C-Sel signal is a two bit control which selects
which coefficient to use at what time. The C-Sel signal can be forced to any value, it can toggle between two coefficients,
or can rotate through all four coefficients. The C-Sel signal is synchronized to the LSBs of the control counter when
toggling between coefficients.
In the cascade mode the A and B paths are used in series as a single path with 32 filter cells. In this mode the
data-out and sum-out outputs of path A are fed into the data-in and sum-in inputs of path B, and the feedback-out of
path B is fed into the feedback-in of path A.
The two paths are independent and can be programmed differently, for example path A can be interpolating
while path B is decimating.
2.7
FILTER CELL
A block diagram of the filter cell is shown in Figure 5.
Forward Delay Control
Reverse Delay Control
Rev
Out
12 Bits
NOTE: The delay circuits can also hold the data
during interpolation.
Z^-(1,2,4)
Rev
In
Data
In
Z^{-(1,2,4) 12 Bits}
CIN
C-Sel
In
Coefficient
I/O
Unsigned Mode
2 Bits
12 Bit Signed
or unsigned Adder
16 Bits
Register 0
Register 1
Register 2
Register 3
14 LSBs
14 Bits
14 by 14 Bit Multiplier
28 Bits
Data
Out
C-Sel
Out
Sum
In
32 Bits
32 Bits
32 Bit Adder
Sum
Out
Figure 5. The Filter Cell
The 12 bit forward and reverse data samples are delayed and then passed to the 12 bit adder. The amount of
delay depends upon the selected filtering modes. In the normal mode the samples are delayed by one clock. In the
decimate by 2 mode the samples are delayed two cycles and in the decimate by four mode the forward samples are
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