GC2011A Datasheet, PDF (36/50 Pages) Texas Instruments – 3.3V DIGITAL FILTER CHIP

GC2011A 3.3V DIGITAL FILTER CHIP
SLWS129A
6.3 CASCADE MODE CONTROL REGISTER
This register controls the cascade mode and the synchronous coefficient storage mode.
ADDRESS 4:
CASCADE_REG
BIT
TYPE
NAME
DESCRIPTION
0 (LSB)
R/W
SYNC_COEF
This bit forces the filter coefficient data to be synchronized to the
system clock before they are stored in the filter cell coefficient
registers.
NOTE: The write cycle control strobe, when storing a coefficient in this
mode, must be active for at least 5 data clock cycles.
1-8
R/W
-
Unused.
9-15(MSB)
R/W
CASCADE
This 7 bit field controls the cascade mode according to the following
table:
CASCADE
DESCRIPTION
(HEX)
10
Dual path mode.
2F
Cascade mode for non-full rate filters
4F
Cascade mode for full rate filters.
To enable the cascade mode the user must also set ANTI_SYM to 1 and FEED_BACK to 08 in APATH_REG1.
In the cascade mode the following control bits are not used:
APATH_REG0:
ACCUM
APATH_REG1:
ODD_SYM
BPATH_REG0:
RATE,NEG_IN, AB_SEL, DELAY_SEL, COEF_SEL
BPATH_REG1:
REV_DELAY, FOR_DELAY
These bits can be treated as “don’t cares”.
The SYNC_COEF mode is only needed when the user is dynamically changing filter coefficients in the
decimate by 4, interpolate by 4 or quarter rate modes. These modes use all four coefficient registers in each filter cell.
Otherwise the user can dynamically change filter coefficients by switching between banks of filter coefficients using the
COEF_SEL control described in Section 6.1.
6.4 COUNTER REGISTER
This register sets the cycle time of the 20 bit internal counter.
ADDRESS 5:
COUNTER_REG
BIT
TYPE
NAME
DESCRIPTION
0-15
R/W
CNT
CNT is the 16 bit counter control word. The counter is preset to
(16*CNT+15) by SI, counts down to zero, and then starts over
again.
A TC terminal count strobe is generated by the counter when it is preset by SI and every time it reaches zero.
The delay from SI to the first TC strobe is set at 8 clocks. The TC strobe will then repeat every 16*(CNT+1) clocks.
6.5 GAIN REGISTER
The gain register controls the filter’s output gain and rounding. Note that the gain setting is synchronized to the
data clock so that gain changes will not cause “glitches” on the output when it is changed. The gain and rounding control
is common to both paths of the chip.
Texas Instruments Incorporated
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