GC2011A Datasheet, PDF (34/50 Pages) Texas Instruments – 3.3V DIGITAL FILTER CHIP

GC2011A 3.3V DIGITAL FILTER CHIP
SLWS129A
The operation of these control bits are illustrated in the following figures.
CK
TIME
0
1
2
3
4
5
6
7
8
9
SI
SO
TC
Full Rate
even
odd even
odd
X0
X1
X2
X3
Half Rate
even
odd
X0
X1
even
X2
Quarter Rate
Full Rate
even
odd
X0
X1
(a) DEL_SEL = 0 (no delay)
even
odd even
odd
X0
X1
X2
X3
Half Rate
even
odd
X0
X1
even
odd
X2
X3
Quarter Rate
even
odd
X0
X1
(b) DEL_SEL = 1 (1 clock delay)
Full Rate
even
odd even
odd
X0
X1
X2
X3
even
odd
even
odd
Half Rate
X0
X1
X2
X3
even
Quarter Rate
X0
odd
even
X1
X2
(c) DEL_SEL = 2 (3 clock delay)
Figure 7. Input Timing
NOTES:
(1) The TC strobe appears 8 clocks after SI and every 16*(CNT+1) clocks thereafter.
(2) The input delays selected by the DEL_SEL control are clock cycle delays, not sample delays. These delays occur
before the input rate circuit captures the samples as shown above.
CK
TIME
0
1
2
SI
Full Rate
odd even
odd
(ACCUM = 0,1, The DAV output is always high)
Half Rate
odd
(ACCUM = 3)
DAV
even
Quarter Rate
(ACCUM = 2)
DAV
3
even
even
4
5
odd even
odd
odd
6
7
odd even
even
8
9
odd even
odd
even
Figure 8. Output Timing
Texas Instruments Incorporated
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