GC2011A Datasheet, PDF (40/50 Pages) Texas Instruments – 3.3V DIGITAL FILTER CHIP

GC2011A 3.3V DIGITAL FILTER CHIP
SLWS129A
6.8 SNAPSHOT START CONTROL REGISTER
This register controls the snapshot trigger settings, the snapshot read modes and the chip’s sync modes.
ADDRESS 10:
SNAP_REGC
BIT
TYPE
NAME
0,1 (LSBs)
R/W
TRIGGER
2,3
R/W
READ_MODE
4
R/W
5
R/W
6
R/W
7
R/W
8,9
R/W
10
R/W
11-15
R/W
ARMED
A_DONE
B_DONE
-
SYNC_OUT
SYNC_OFF
-
DESCRIPTION
This control sets the trigger condition which will start a snapshot once
the ARMED bit is set. The trigger conditions are to start:
TRIGGER
DESCRIPTION
0
immediately,
1
when the SN strobe is received,
2
when the SI strobe is received,
3
when the TC strobe is received.
Selects whether words or bytes are read from the snapshot memory
according to:
READ_MODE
DESCRIPTION
0,2
read words,
1
read the least significant bytes
3
read the most significant bytes
When reading bytes, the bytes are placed in the LSBs of the 16 bit
control word and sign extended.
The user sets this bit to arm the snapshot memory so that it will
start on the next trigger condition. The chip clears this bit when
the trigger occurs.
This bit goes high when the A-half snapshot is complete. This bit
must be cleared by writing a zero to it.
This bit goes high when the B-half snapshot is complete. This bit
must be cleared by writing a zero to it.
unused
This two bit field selects the sync output (SO) source as:
SYNC_OUT
DESCRIPTION
0
SI delayed by 4 clocks (SYNC_OFF=0),
1
TC,
2
OS,
3
never
This bit disables the sync input to the chip. The counter will free
run when this bit is high
unused
6.9 ONE SHOT ADDRESS
The one shot pulse is generated on the OS pin by writing to address 11. This is a write-only address. The data
written to it is irrelevant.
ADDRESS 11:
ONE_SHOT
Texas Instruments Incorporated
- 36 -
This document contains information which may be changed at any time without notice