GC2011A Datasheet, PDF (37/50 Pages) Texas Instruments – 3.3V DIGITAL FILTER CHIP

GC2011A 3.3V DIGITAL FILTER CHIP
SLWS129A
ADDRESS 6:
GAIN_REG
BIT
TYPE
NAME
0-3
R/W
4-7
R/W
8-14
R/W
F
S
ROUND
15 (MSB)
R/W
-
DESCRIPTION
The 4 bit gain fraction.
The 4 bit gain exponent.
Controls the output rounding according to the following table:
ROUND
DESCRIPTION
(HEX)
00
Truncate
01
Round to the 8 MSBs
02
Round to the 10 MSBs
04
Round to the 12 MSBs
08
Round to the 14 MSBs
10
Round to the 16 MSBs
20
Round to the 20 MSBs
40
Round to the 24 MSBs
Unused
The chip’s output gain is set using F and S according to the following formula:
GAIN =2^(S-20)(1+F/16)(DC_GAIN)
Where DC_GAIN is the sum of the filter coefficients. Unity gain, according to this formula, will map the MSB of the12 bit
input data (AI11 or BI11) into the MSB of the selected output word (AO15 or BO15).
The 32 bit filter path output is rounded to the number of most significant bits selected by the round control. The
gain circuit output is saturated to plus or minus full scale if the GAIN setting causes an overflow. The AOF or BOF output
pins will go high whenever an overflow is detected in the A-Path or B-path gain circuit.
For example: If the DC gain of the filter coefficients is 2¹⁵ (i.e., the sum of the coefficients is 2¹⁵), then the
overall gain of the filter can be set to unity by setting S to 5 and F to 0.
Texas Instruments Incorporated
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This document contains information which may be changed at any time without notice