GC2011A Datasheet, PDF (12/50 Pages) Texas Instruments – 3.3V DIGITAL FILTER CHIP

GC2011A 3.3V DIGITAL FILTER CHIP
SLWS129A
2.4 INPUT MUX
The input multiplexor circuit performs three functions: It allows the user to select which data source to use as
the input to the two filter paths, it sets the input data rate, and it optionally delays the data. The controls for the input
selection, the input rate, and the data delay are independent for the A and B filter paths.
The input circuit allows the user to select either the A-input, the B-input or the 12 LSBs of the counter for the
filter path’s input. Typically the A-input will feed the A-path and the B-input will feed the B-path. The counter input is
selected for diagnostics.
If the input rate is less than the clock rate, as is the case for the interpolation modes, the half rate I/O modes
and the quarter rate I/O modes, then the input circuit can be programmed to hold every-other or every-fourth input
sample.
The input delay can be set to 0, 1 or 3 clock cycles. These delays are typically set to zero, but are necessary
in the real to complex and complex to real conversion modes.
The control and timing information for the input circuit are described in Section 6.1.
2.5 INPUT NEGATION
The data from the input circuit can be optionally negated by the input negate circuit. The input negation circuit
allows the user to negate all samples, the even time samples (i.e., every other input), or the odd time samples. This
circuit is used to mix the input data down by F_S/4 in the real to complex conversion mode.
The input negation controls are described in Section 6.1.
2.6 A/B FILTER PATHS
A block diagram of the 16 cell filter path is shown in Figure 4.
Feedback Controls
Cascade Mode
Delay Controls
Delay Controls
Delay Controls
Feedback^a
In
Feedback^b _{12 Bits}
Out
Rev
Out
Data
In
12 Bits _Data
In
C-Sel
In
2 Bits _C-Sel
In
Sum^b
In
32 Bits _Sum
In
Rev
In
Data
Out
C-Sel
Out
Sum
Out
FILTER CELL #1
Rev
Out
Data
In
Rev
In
Data
Out
C-sel
In
C-Sel
Out
Sum
In
Sum
Out
FILTER CELL #2
•••
Rev
Out
Data
In
Rev
In
Data
Out
C-Sel
In
Sum
In
C-Sel
Out
Sum ^{32 Bits}
Out
FILTER CELL #16
FEEDBACK
CIRCUIT
Data^a
Out
Sum
Out
KEY: ^a = These signals are unique to the A-Path circuit
b _{= These signals are unique to the B-Path circuit}
Figure 4. 16 Cell Filter Path Block Diagram
Only the data paths through the filter cells are shown. The coefficient interfaces are not shown. Each filter path
contains 16 filter cells and a data feedback circuit. The filter cell contains a multiplier-adder structure described in the
next section. The feedback circuit delays and feeds back the data output to provide the reverse data used in the
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