GC2011A Datasheet, PDF (5/50 Pages) Texas Instruments – 3.3V DIGITAL FILTER CHIP

GC2011A 3.3V DIGITAL FILTER CHIP
SLWS129A
GC2011A DATASHEET
1.0 KEY FEATURES
• Improved 3.3 volt, higher speed, GC2011
replacement
• 106 million samples per second (MSPS) input
rate
• Dual inputs for complex, dual path or double
rate input processing
• 2’s Complement to offset binary conversion
• 12 bit or 24 bit data, 14 bit coefficients
• 8, 10, 12, 14, 16, 20 or 24 bit outputs
• 32 bit internal precision
• 32 multiply-add filter cells
• Snapshot memory for adaptive filtering
• 64 taps with even or odd symmetry
• 128 tap decimate by 2
• 256 tap decimate by 4
• 128 tap interpolate by 2 or 4
• 128 taps for 1/2 rate I/O
• 256 taps for 1/4 rate I/O
• 200 MSPS real to 100 MSPS complex
conversion mode
• Real to complex or complex to real
conversion modes
• Snapshot memory for adaptive filter
update calculations
• Gain adjust in 0.5 dB steps
• Microprocessor interface for control,
output, and diagnostics
• Built in diagnostics
• 1.6 Watt at 80 MHz, 3.3 volts
• 160 pin quad flat pack package
• 160 pin ball grid array package
1.1 BLOCK DIAGRAM
A block diagram illustrating the major functions of the chip is shown in Figure 1
AIN ^{12 bits}
BIN ^{12 bits}
C
A
RE
WE
CE
16 bits
9 bits
12 bits
32 bits
Feedback In
Data In
A-PATH ^{Data Out 12 bits}
(16 FILTER CELLS)
Sum In
Sum Out ^{32 bits}
+/-1
(CASCADE MODE ONLY)
12 bits
32 bits
Feedback Out
Data In
B-PATH ^{Data Out 12 bits}
(16 FILTER CELLS)
Sum In
Sum Out ^{32 bits}
+/-1
CASCADE MODE
CONTROL INTERFACE
MODE CONTROLS
SNAPRAM READ
COEFFICIENT READ/WRITE
AIN ^{12 bits}
BIN ^{12 bits}
AOUT ^{16 bits}
BOUT ^{16 bits}
ADD
+/-1
32 bits
16 bits
16 bits
AOUT
GAIN
32 bits
24 bits
2^-12 _{24 BIT MODE}
+/-1
16 bits
BOUT
SNAPSHOT RAM
-DUAL 128 BY 16 BIT MODE
-DUAL 256 BY 8 BIT MODE
-SINGLE 256 BY 16 BIT MODE
-SINGLE 512 BY 8 BIT MODE
Figure 1. GC2011A Block Diagram
Texas Instruments Incorporated
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