GC2011A Datasheet, PDF (22/50 Pages) Texas Instruments – 3.3V DIGITAL FILTER CHIP

GC2011A 3.3V DIGITAL FILTER CHIP
SLWS129A
3.6 INTERPOLATION
Another common filtering application is to increase the signal’s sample rate through interpolation. Interpolation
is performed by inserting zeros between input samples so as to double or quadruple the sample rate, and then to low
pass filter the result. In the interpolation modes the GC2011A chip automatically zero pads the input as it low pass filters
the result. The interpolation modes double or quadruple the number of taps implemented by each filter cell. The input
sample rate is one half or one fourth the clock rate as shown in Figure 6. The output rate is at the clock rate.
Table 7: Interpolation Mode Control Register Settings
I/O Rates
In
Out
Symmetr
y
Dual Path or
Cascaded
# of Taps
(N)
A-PATH
REG0 REG1
B-PATH
REG0 REG1
Cascade
REG
Latency
Tap
Storage^a
Full Double Odd
Dual
63
20D8 6108 20D8 6181 2000
44
DF
Half Full
None
Dual
32
6388 2E00 4388 2E00 2000
46
HR
Cascaded
64
6388 2E28 4388 2E00 5E00
62
Odd
Dual
63
6388 2E91 4388 2E91 2000
46
Cascaded
127 6388 2EA8 4388 2E91 5E00
62
Quar- Full
None
Dual
64
A200 0000 8200 0000 2000
46
See
ter
Cascaded
128 A200 0028 9200 0000 5E00
62
Text
a. HR = Use half rate coefficient storage as described in Section 3.2. DF = Use double to full rate storage in Section 3.8.
In the interpolate by 4 (quarter rate in, full rate out) mode the coefficient storage is reversed within each filter
cell. The interpolate by 4 coefficients, h(k), are stored in:
memory address BASE+k+0 if k modulo-4 is 0
memory address BASE+k+2 if k modulo-4 is 1
memory address BASE+k+0 if k modulo-4 is 2
memory address BASE+k-2 if k modulo-4 is 3
where BASE is 128 for A-path or cascaded filters and is 192 for B-path filters. For example,
Coefficient Memory address
h(0)
128+0
h(1)
128+3
h(2)
128+2
h(3)
128+1
h(4)
128+4
h(5)
128+7
h(6)
128+6
h(7)
128+5
h(8)
128+8
h(9)
128+11
etc.
Texas Instruments Incorporated
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