GC2011A Datasheet, PDF (17/50 Pages) Texas Instruments – 3.3V DIGITAL FILTER CHIP

GC2011A 3.3V DIGITAL FILTER CHIP
SLWS129A
3.0 FILTERING MODES
This Section describes common filtering modes and how to configure the chip to implement them. Unless
otherwise indicated, only the A-path, B-path and cascade mode control register values are given. The counter, gain,
output, and snapram control registers can be given the default values listed in Table 1 below.
Table 1: Default Control Register Settings
REGISTER
COUNTER
GAIN
OUTPUT
SNAP_REGA
SNAP_REGB
SNAP_REGC
DEFAULT
0
1030
0
0
0
0
COMMENT
Don’t care
See Section 6.5
See Section 6.6
See Sections 6.7 and 6.8 to
configure the snapshot memory
The default settings configure the chip to:
• Use the A-in pins for the cascaded mode data input and the B-out pins for the cascaded
mode data output. The cascaded mode results can be output on the A-out pins by
setting the OUTPUT register to 0008_HEX.
• Round the outputs to 16 bits.
∑ ^{• Give an input to output gain of 2–13 h(k)}
The input to output latency is given for each of the modes. The latency is due to pipeline delays and is defined
as the delay from x₀ (see Figure 6-a) to the first filter output affected by x₀. One can measure this delay by clearing all
of the filter taps except for the first tap and using an impulse as the data input. The latency is then defined as the delay
in clock cycles (not data samples) from the impulse in to the impulse out
The modes described in this Section have been configured so that the input and output timing is as shown in
Figure 6. In the half rate and quarter rate modes the inputs must be synchronized with SI as shown. The output timing
shows how the output samples are generated relative to SI.
CK
TIME
0
1
2
3
4
5
6
7
8
9
SI
Full Rate
X0
Half Rate
X0
Quarter Rate
X0
Full Rate
Half Rate
Quarter Rate
(a) INPUT TIMING
(b) OUTPUT TIMING
Figure 6. I/O Timing
Texas Instruments Incorporated
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