GC2011A Datasheet, PDF (33/50 Pages) Texas Instruments – 3.3V DIGITAL FILTER CHIP

GC2011A 3.3V DIGITAL FILTER CHIP
SLWS129A
6.1 A-PATH AND B-PATH CONTROL REGISTER 0
Control registers APATH_REG0 and BPATH_REG0 are identical and are described here.
ADDRESS 0:
APATH_REG0
ADDRESS 2:
BPATH_REG0
BIT
0,1 (LSBs)
TYPE
R/W
2
R/W
3-7
R/W
8,9
R/W
10-12
R/W
13
R/W
14,15(MSB)
R/W
NAME
ACCUM
UNSIGNED
COEF_SEL
RATE
NEG_IN
AB_SEL
DELAY_SEL
DESCRIPTION
This two bit field controls the accumulator according to the
following table:
ACCUM
DESCRIPTION
0,1
don’t accumulate (full rate output)
2
accumulate 4 sums (quarter rate)
3
accumulate 2 sums (half rate)
The ACCUM control also sets the output data rate as shown in
Figure 8.
The filter cell adder (See Figure 5) is in the unsigned mode when
this bit is set.
This five bit field controls how the four coefficients are used
within the filter cells. The controls are:
COEF_SEL
DESCRIPTION
(HEX)
1B
use coefficient reg 1
1F
use coefficient reg 3
11
toggle between registers 0 and 1
15
toggle between registers 2 and 3
00
cycle through all four registers
This two bit field sets the input rate as follows: (See Figure 7)
RATE
DESCRIPTION
0,1
full rate input
2
quarter rate input
3
half rate input
These three bits control the input sample negation as follows:
NEG_IN
DESCRIPTION
0
don’t negate
1
negate even time full rate samples
2
negate odd time half rate samples
3
negate even time quarter rate samples
4
always negate
5
negate odd time full rate samples
6
negate even time half rate samples
7
negate odd time quarter rate samples
where the definition of even and odd time samples is shown in
Figure 7.
Select input A-in when high, B-in when low.
Selects the input delay or counter input as follows:
DELAY_SEL
DESCRIPTION
0
no delay
1
one clock delay
2
3 clock delay
3
use counter as input
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