GC2011A Datasheet, PDF (19/50 Pages) Texas Instruments – 3.3V DIGITAL FILTER CHIP

GC2011A 3.3V DIGITAL FILTER CHIP
SLWS129A
3.2 HALF RATE
The number of taps in the filter can be doubled if the data rate into and out of the chip is one half the clock rate.
In this mode each filter cell stores two filter coefficients and performs two tap multiplications per output sample. The
cells’ delay lines are adjusted so that two feed-forward and two feedback data samples are delayed within each filter
cell. The accumulator at the end of the filter path sums the products to give the half rate output. The chip is configured
in the half rate mode using the control settings shown in Table 3.
Table 3: Half Rate Mode Control Register Settings
Symmetry
None
Even
Odd
Dual Path or
Cascaded
Dual
Cascaded
Dual
Cascaded
Dual
Cascaded
# of Taps
(N)
32
64
64
128
63
127
A-PATH
REG0
638B
638B
638B
638B
638B
638B
REG1
AE00
AE28
A218
A228
A294
A2A8
B-PATH
REG0
438B
438B
438B
438B
438B
438B
REG1
AE00
AE00
A218
A218
A294
A294
Cascade
Latency
REG
2000
46
5E00
62
2000
46
5E00
62
2000
46
5E00
62
The coefficients can be stored in coefficient registers 0 and 1 in each filter cell or registers 2 and 3. To store
coefficients h(k) in registers 0 and 1 of each filter cell use memory addresses:
BASE+2*k
for k even and
BASE+2*k-1
for k odd.
To use registers 2 and 3 store the coefficients in addresses
BASE+2*k+2
for k even and
BASE+2*k+1
for k odd.
Where BASE is 128 for A-path or cascaded filters, and is 192 for B-path filters.
To switch from using registers 0 and 1 to registers 2 and 3 add 0020_HEX to the REG0 values shown in Table
3. Register switching is synchronized by the chip to the clock in order to prevent unwanted transients.
Texas Instruments Incorporated
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