GC2011A Datasheet, PDF (31/50 Pages) Texas Instruments – 3.3V DIGITAL FILTER CHIP

GC2011A 3.3V DIGITAL FILTER CHIP
SLWS129A
5.0
PIN DESCRIPTIONS
SIGNAL
AI[0:11]
BI[0:11]
CK
CKEN
SI
SN
AO[0:15]
BO[0:15]
AOE
BOE
DAV
AOF
BOF
SO
C[0:15]
A[0:8]
RE, WE, CE
DESCRIPTION
A-PATH INPUT DATA. Active high
The 12 bit two’s complement input samples for path A. New samples are clocked into the chip on
the rising edge of the clock.
B-PATH INPUT DATA. Active high
The 12 bit two’s complement input samples for path B. New samples are clocked into the chip on
the rising edge of the clock.
CLOCK INPUT. Active high
The clock input to the chip. The AI, BI, SI, SN and CKEN signals are clocked into the chip on the
rising edge of this clock. The AO, BO, DAV, AOF, BOF and SO signals are clocked out on the
rising edge of this clock.
CLOCK ENABLE INPUT. Active low
The clock enable input to the chip. This signal is gated with CK to generate the chip’s internal clock.
CKEN is clocked into the chip on the rising edge of CK and will enable or disable the following clock
edge. A low level on CKEN enables the clock edge.
SYNC INPUT. Active low
The sync input to the chip. All timers, accumulators, and control counters are, or can be,
synchronized to SI. This sync is clocked into the chip on the rising edge of the clock.
SNAPSHOT SYNC. Active low
The snapshot sync is provided to synchronously start the data snapshot. This signal is clocked into
the chip on the rising edge of the clock.
A-PATH OUTPUT DATA. Active high
The A-path output samples are output as 16 bit words on these pins. The bits are clocked out on
the rising edge of the clock.
B-PATH OUTPUT DATA. Active high
The B-path output samples are output as 16 bit words on these pins. The bits are clocked out on
the rising edge of the clock.
A-PATH OUTPUT ENABLE. Active low
The A[0:15] and AOF output pins are put into a high impedance state when this pin is high.
B-PATH OUTPUT ENABLE. Active low
The B[0:15] BOF output pins are put into a high impedance state when this pin is high.
DATA VALID STROBE. Programmable active high or low level
This strobe is output synchronous with the A and B data words. The strobe is used in the decimate,
half rate, or quarter rate output modes to indicate when the output words are valid. The high/low
polarity of the strobe is programmable.
A-PATH OVERFLOW Active high
This signal goes high for one clock cycle each time there is an overflow in the A-path gain output.
B-PATH OVERFLOW Active high
This signal goes high for one clock cycle each time there is an overflow in the B-path gain output.
SYNC OUT. Active low
This signal is either the input sync SI delayed by 4 clock cycles, the one shot sync OS, or the
internal counter’s terminal count strobe TC.
CONTROL DATA I/O BUS. Active high
This is the 16 bit control data I/O bus. Control register contents are loaded into the chip or read from
the chip through these pins. The chip will only drive these pins when CE and RE are low and WE
is high.
CONTROL ADDRESS BUS. Active high
These pins are used to address the control registers, coefficient registers, and the snapram
memory within the chip.
READ, WRITE, and CHIP ENABLE STROBES. active low
These pins control the reading and writing of control data. If RE is held low the chip will operate in
the GC2011 read/write mode, where WE is the GC2011’s R/W control and CE is the GC2011’s CS
control strobe. (See Section 2.2)
Texas Instruments Incorporated
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This document contains information which may be changed at any time without notice