TL16C752B-EP Datasheet, PDF (31/35 Pages) Texas Instruments – 3.3-V DUAL UART WITH 64-BYTE FIFO

TL16C752B-EP
3.3-V DUAL UART WITH 64-BYTE FIFO
PRINCIPLES OF OPERATION
SGLS153 – FEBRUARY 2003
Table 18. Transmission Control Register (TCR) Bit Settings
BIT NO.
3:0
7:4
BIT SETTINGS
RCV FIFO trigger level to halt transmission (0–60)
RCV FIFO trigger level to resume transmission (0–60)
TCR trigger levels are available from 0–60 bytes with a granularity of four.
NOTE:
TCR can only be written to when EFR[4] = 1 and MCR[6] = 1. The programmer must program the
TCR such that TCR[3:0] > TCR[7:4]. There is no built-in hardware check to make sure this condition
is met. Also, the TCR must be programmed with this condition before Auto-RTS or software flow
control is enabled to avoid spurious operation of the device.
trigger level register (TLR)
The trigger level register is an 8-bit register that is pulsed to store the transmit and received FIFO trigger levels
used for DMA and interrupt generation. Trigger levels from 4–60 can be programmed with a granularity of 4.
Table 19 shows the trigger level register bit settings.
Table 19. Trigger Level Register (TLR) Bit Settings
BIT NO.
3:0
7:4
BIT SETTINGS
Transmit FIFO trigger levels (4–60), number of spaces available
RCV FIFO trigger levels (4–60), number of characters available
NOTE:
TLR can only be written to when EFR[4] = 1 and MCR[6] = 1. If TLR[3:0] or TLR[7:4] are 0, the
selectable trigger levels via the FIFO control register (FCR) are used for the transmit and receive
FIFO trigger levels. Trigger levels from 4–60 bytes are available with a granularity of four. The TLR
should be programmed for N/4, where N is the desired trigger level.
When the trigger level setting in TLR is zero, the TL16C752B-EP uses the trigger level setting defined in FCR.
If TLR has a nonzero trigger level value, the trigger level defined in FCR is discarded. This applies to both the
transmit FIFO and receive FIFO trigger level setting.
FIFO ready register
The FIFO ready register provides real-time status of the transmit and receive FIFOs of both channels. Table 20
shows the FIFO ready register bit settings. The trigger level mentioned below refers to the setting in either FCR
(when TLR value is zero), or TLR (when it has a nonzero value).
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