TL16C752B-EP Datasheet, PDF (29/35 Pages) Texas Instruments – 3.3-V DUAL UART WITH 64-BYTE FIFO

TL16C752B-EP
3.3-V DUAL UART WITH 64-BYTE FIFO
PRINCIPLES OF OPERATION
SGLS153 – FEBRUARY 2003
interrupt enable register (IER)
The interrupt enable register (IER) enables each of the six types of interrupt, receiver error, RHR interrupt, THR
interrupt, Xoff received, or CTS/RTS change of state from low-to-high. The INT output signal is activated in
response to interrupt generation. Table 14 shows the IER bit settings.
Table 14. Interrupt Enable Register (IER) Bit Settings
BIT NO.
0
1
BIT SETTINGS
0 = Disable the RHR interrupt
1 = Enable the RHR interrupt
0 = Disable the THR interrupt
1 = Enable the THR interrupt
2
0 = Disable the receiver line status interrupt
1 = Enable the receiver line status interrupt
3
0 = Disable the modem status register interrupt
1 = Enable the modem status register interrupt
4
0 = Disable sleep mode
1 = Enable sleep mode
5
0 = Disable the Xoff interrupt
1 = Enable the Xoff interrupt
6
0 = Disable the RTS interrupt
1 = Enable the RTS interrupt
7
0 = Disable the CTS interrupt
1 = Enable the CTS interrupt
NOTE: IER[7:4] can only be modified if EFR[4] is set, i.e., EFR[4] is a write enable.
Re-enabling IER[1] does not cause a new interrupt if the THR is below the
threshold.
interrupt identification register (IIR)
The interrupt identification register is a read-only 8-bit register, which provides the source of the interrupt in a
prioritized manner. Table 15 shows the IIR bit settings.
Table 15. Interrupt Identification Register (IIR) Bit Settings
BIT NO.
0
3:1
4
5
7:6
BIT SETTINGS
0 = A interrupt is pending
1 = No interrupt is pending
3-Bit encoded interrupt. See Table 14.
1 = Xoff/Special character has been detected.
CTS/RTS low-to-high change of state.
Mirror the contents of FCR[0]
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