TL16C752B-EP Datasheet, PDF (11/35 Pages) Texas Instruments – 3.3-V DUAL UART WITH 64-BYTE FIFO

TL16C752B-EP
3.3-V DUAL UART WITH 64-BYTE FIFO
SGLS153 – FEBRUARY 2003
functional description (continued)
polled mode operation
In polled mode (IER[3:0]=0000) the status of the receiver and transmitter can be checked by polling the line
status register (LSR). This mode is an alternative to the FIFO interrupt mode of operation where the status of
the receiver and transmitter is automatically known by means of interrupts sent to the CPU. Figure 6 shows FIFO
polled mode operation.
Processor
IOW/IOR
LSR
IER
0000
THR
RHR
Figure 6. FIFO Polled Mode Operation
DMA signalling
There are two modes of DMA operation: DMA mode 0 or 1, selected by FCR[3].
In DMA mode 0 or FIFO disable (FCR[0]=0) DMA occurs in single character transfers. In DMA mode 1 multi-
character (or block) DMA transfers are managed to relieve the processor for longer periods of time.
single DMA transfers (DMA mode0/FIFO disable)
Transmitter: When empty, the TXRDY signal becomes active. TXRDY goes inactive after one character has
been loaded into it.
Receiver: RXRDY is active when there is at least one character in the FIFO. It becomes inactive when the
receiver is empty.
Figure 7 shows TXRDY and RXRDY in DMA mode0/FIFO disable.
TX
RX
TXRDY
RXRDY
wrptr
At Least One
Location Filled
rdptr
At Least One
Location Filled
TXRDY
wrptr
FIFO Empty
RXRDY
rdptr
FIFO Empty
Figure 7. TXRDY and RXRDY in DMA Mode 0/FIFO Disable
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