TL16C752B-EP Datasheet, PDF (2/35 Pages) Texas Instruments – 3.3-V DUAL UART WITH 64-BYTE FIFO

TL16C752B-EP
3.3-V DUAL UART WITH 64-BYTE FIFO
SGLS153 – FEBRUARY 2003
description (continued)
The TL16C752B-EP is available in a 48-pin PT (LQFP) package.
PACKAGE
(TOP VIEW)
D5
D6
D7
RXB
RXA
TXRDYB
TXA
TXB
OPB
CSA
CSB
NC
48 47 46 45 44 43 42 41 40 39 38 37
1
36
2
35
3
34
4
33
5
32
6
31
7
30
8
29
9
28
10
27
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
RESET
DTRB
DTRA
RTSA
OPA
RXRDYA
INTA
INTB
A0
A1
A2
NC
NC – No internal connection
AVAILABLE OPTIONS
TA
– 40°C to 110°C
PACKAGE
TL16C752BTPTREP
Terminal Functions
TERMINAL
NAME
NO.
A0
28
A1
27
A2
26
CDA, CDB 40, 16
CSA, CSB 10, 11
CTSA,
CTSB
38, 23
I/O
DESCRIPTION
I Address 0 select bit. Internal registers address selection
I Address 1 select bit. Internal registers address selection
I Address 2 select bit. Internal registers address selection
Carrier detect (active low). These inputs are associated with individual UART channels A and B. A low on these
I pins indicates that a carrier has been detected by the modem for that channel. The state of these inputs is reflected
in the modem status register (MSR).
Chip select A and B (active low). These pins enable data transfers between the user CPU and the TL16C752B-EP
I for the channel(s) addressed. Individual UART sections (A, B) are addressed by providing a low on the respective
CS A and CS B pins.
Clear to send (active low). These inputs are associated with individual UART channels A and B. A logic low on
I
the CTS pins indicates the modem or data set is ready to accept transmit data from the TL16C752B-EP. Status
can be tested by reading MSR bit 4. These pins only affect the transmit and receive operations when auto CTS
function is enabled through the enhanced feature register (EFR) bit 7, for hardware flow control operation.
2
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