TL16C752B-EP Datasheet, PDF (17/35 Pages) Texas Instruments – 3.3-V DUAL UART WITH 64-BYTE FIFO

TL16C752B-EP
3.3-V DUAL UART WITH 64-BYTE FIFO
SGLS153 – FEBRUARY 2003
timing requirements T_A = –40°C to 110°C, V_CC = 3.3 V ± 10% (unless otherwise noted)
(see Figures 12–19)
PARAMETER
td1
IOR delay from chip select
td2
Read cycle delay
td3
Delay from IOR to data
td4
Data disable time
td5
IOW delay from chip select
td6
Write cycle delay
td7
Delay from IOW to output
td8
Delay to set interrupt from MODEM input
td9
Delay to reset interrupt from IOR
td10
Delay from stop to set interrupt
td11
Delay from IOR to reset interrupt
td12
Delay from stop to interrupt
td13
Delay from initial INT reset to transmit start
td14
Delay from IOW to reset interrupt
td15
Delay from stop to set RXRDY
td16
Delay from IOR to reset RXRDY
td17
Delay from IOW to set TXRDY
td18
Delay from start to reset TXRDY
td19
Delay between successive assertion of IOW and IOR
th1
Chip select hold time from IOR
th2
Chip select hold time from IOW
th3
Data hold time
th4
Address hold time
th5
Hold time from XTAL1 clock ↓ to IOW or IOR release
tp1, tp2
Clock cycle period
tp3
Oscillator/clock speed
t(RESET) Reset pulse width
tsu1
Address setup time
tsu2
Data setup time
tsu3
Setup time from IOW or IOR assertion to XTAL1 clock ↑
tw1
IOR strobe width
tw2
IOW strobe width^§
† _{Baud rate}
‡ _{tp(I) = input clock period}
TEST CONDITIONS
100-pF load
100-pF load
100-pF load
100-pF load
VCC = 3 V
MIN
0
2tp(I)^‡
10
2tp(I)^‡
8
0
0
15
0
20
20
200
0
16
20
2tp(I)^‡
2tp(I)^‡
MAX
28.5
15
50
70
70
1Rclk
70
100
24
70
1
1
70
16
4P^‡
48
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
†
ns
ns
†
ns
Clock
µs
ns
†
†
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
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