TL16C752B-EP Datasheet, PDF (22/35 Pages) Texas Instruments – 3.3-V DUAL UART WITH 64-BYTE FIFO

TL16C752B-EP
3.3-V DUAL UART WITH 64-BYTE FIFO
SGLS153 – FEBRUARY 2003
Start
Bit
Data Bits (5–8)
Stop
Bit
TX (A–B)
D0 D1 D2 D3 D4 D5 D6 D7
5 Data Bits
6 Data Bits
7 Data Bits
Parity
Bit
IOW
Active
D0–D7
TXRDY (A–B)
Byte 32
td18
td17
Trigger
Lead
Figure 20. Transmit Ready Timing in FIFO Mode
timing error condition
Texas Instruments has discovered a timing anomaly in the TL16C752B-EP.
The problem only occurs under a special set of circumstances (non-FIFO mode) and can be worked around
by using certain timing. Depending on actual system application, some customers may not see this problem.
There are currently no plans to fix this problem, because it is felt that it is a minor issue. It is unlikely the device
is used in non-FIFO mode, and if it is, the software workaround does not have a significant impact on throughput
(< 1%).
problem description
When using the non-FIFO (single byte) mode of operation, it is possible that valid data could be reported as
available by either the line status register (LSR) or the interrupt identification register (IIR), before the receiver
holding register (RHR) can be read. In other words, the loading of valid data in RHR may be delayed when the
part operates in non-FIFO mode. The data in the RHr is valid after a delay of one baud-clock period after the
update of the LSR or IIR. The baud-clock runs at 16X the baud rate. The following table is a sample of baud
rates and associated required delays. Depending on the operating environment, this time may well be
transparent to the system, e.g., less than the context switch time of the interrupt service routine.
This problem does not exist when using FIFO mode (64 byte) mode of operation.
BAUDRATE (BIT PER SECOND)
1200
2400
4800
9600
19200
38400
57600
115200
1000000
REQUIRED DELAY (µs)
52.1 µs
26 µs
13 µs
6.5 µs
3.3 µs
1.6 µs
1.1 µs
0.5 µs
62.5 ns
22
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265