TL16C752B-EP Datasheet, PDF (28/35 Pages) Texas Instruments – 3.3-V DUAL UART WITH 64-BYTE FIFO

TL16C752B-EP
3.3-V DUAL UART WITH 64-BYTE FIFO
SGLS153 – FEBRUARY 2003
PRINCIPLES OF OPERATION
modem control register (MCR)
The MCR controls the interface with the modem, data set, or peripheral device that is emulating the modem.
Table 12 shows the modem control register bit settings.
Table 12. Modem Control Register (MCR) Bit Settings
BIT NO.
BIT SETTINGS
0
0 = Force DTR output to inactive (high)
1 = Force DTR output to active (low)
In loopback controls MSR[5].
1
0 = Force RTS output to inactive (high)
1 = Force RTS output to active (low)
In loopback controls MSR[4]
If Auto-RTS is enabled the RTS output is controlled by hardware flow control
2
0 Disables the FIFO Rdy register
1 Enable the FIFO Rdy register
In loopback controls MSR[6].
3
0 = Forces the INT(A – B) outputs to 3-state and OP output to high state
1 = Forces the INT(A – B) outputs to the active state and OP output to low state
In loopback controls MSR[7].
4
0 = Normal operating mode
1 = Enable local loopback mode (internal)
In this mode the MCR[3:0] signals are looped back into MSR[3:0] and the TX output is looped back to the RX input internally.
5
0 = Disable Xon any function
1 = Enable Xon any function
6
0 = No action
1 = Enable access to the TCR and TLR registers
7
0 = Divide by one clock input
1 = Divide by four clock input
NOTE: MCR[7:5] can only be modified when EFR[4] is set i.e., EFR[4] is a write enable.
modem status register (MSR)
The modem status register is an 8-bit register that provides information about the current state of the control
lines from the modem, data set, or peripheral device to the processor. It also indicates when a control input from
the modem changes state. Table 13 shows the modem status register bit settings per channel.
Table 13. Modem Status Register (MSR) Bit Settings
BIT NO.
BIT SETTINGS
0
Indicates that the CTS input (or MCR[1] in loopback) has changed state. Cleared on a read.
1
Indicates that the DSR input (or MCR[0] in loopback) has changed state. Cleared on a read.
2
Indicates that the RI input (or MCR[2] in loopback) has changed state from low to high. Cleared on a read.
3
Indicates that the CD input (or MCR[3] in loopback) has changed state. Cleared on a read.
4
This bit is the complement of the CTS input during normal mode. During internal loopback mode, it is equivalent to MCR[1].
5
This bit is the complement of the DSR input during normal mode. During internal loopback mode, it is equivalent to MCR[0].
6
This bit is the complement of the RI input during normal mode. During internal loopback mode, it is equivalent to MCR[2].
7
This bit is the complement of the CD input during normal mode. During internal loopback mode, it is equivalent to MCR[3].
NOTE: The primary inputs RI, CD, CTS, DSR are all active low, but their registered equivalents in the MSR and MCR (in loopback) registers are
active high.
28
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265