TL16C752B-EP Datasheet, PDF (20/35 Pages) Texas Instruments – 3.3-V DUAL UART WITH 64-BYTE FIFO

TL16C752B-EP
3.3-V DUAL UART WITH 64-BYTE FIFO
SGLS153 – FEBRUARY 2003
Start
Bit
Data Bits (5–8)
Stop
Bit
RX (A–B)
RXRDY (A–B)
RXRDY
D0 D1 D2 D3 D4 D5 D6 D7
Parity
Bit
Next
Data
Start
Bit
td15
Active
Data
Ready
td16
Active
IOR
Figure 16. Receive Ready Timing in Non-FIFO Mode
RX (A–B)
RXRDY (A–B)
RXRDY
IOR
Start
Bit
Data Bits (5–8)
Stop
Bit
D0 D1 D2 D3 D4 D5 D6 D7
Parity
Bit
First Byte
That Reaches
the Trigger
Level
td15
Active
Data
Ready
td16
Active
Figure 17. Receive Timing in FIFO Mode
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