TL16C752B-EP Datasheet, PDF (25/35 Pages) Texas Instruments – 3.3-V DUAL UART WITH 64-BYTE FIFO

TL16C752B-EP
3.3-V DUAL UART WITH 64-BYTE FIFO
PRINCIPLES OF OPERATION
SGLS153 – FEBRUARY 2003
receiver holding register (RHR) and the receiver shift register (RSR)
The receiver section consists of the receiver holding register (RHR) and the receiver shift register (RSR). The
RHR is actually a 64-byte FIFO. The RSR receives serial data from the RX terminal. The data is converted to
parallel data and moved to the RHR. The receiver section is controlled by the line control register. If the FIFO
is disabled, location zero of the FIFO is used to store the characters. (Note, in this case characters are
overwritten if overflow occurs.) If overflow occurs, characters are lost. The RHR also stores the error status bits
associated with each character.
transmit holding register (THR) and the transmit shift register (TSR)
The transmitter section consists of the transmit holding register (THR) and the transmit shift register (TSR). The
THR is actually a 64-byte FIFO. The THR receives data and shifts it into the TSR, where it is converted to serial
data and moved out on the TX terminal. If the FIFO is disabled, the FIFO is still used to store the byte. Characters
are lost if overflow occurs.
FIFO control register (FCR)
The FIFO control register is a write-only register, which is used for enabling the FIFOs, clearing the FIFOs,
setting transmitter and receiver trigger levels, and selecting the type of DMA signalling. Table 9 shows the FCR
bit settings.
Table 9. FIFO Control Register (FCR) Bit Settings
BIT NO.
BIT SETTINGS
0
0 = Disable the transmit and receive FIFOs
1 = Enable the transmit and receive FIFOs
1
0 = No change
1 = Clears the receive FIFO and resets counter logic to zero. Returns to zero after clearing FIFO.
2
0 = No change
1 = Clears the transmit FIFO and resets counter logic to zero. Returns to zero after clearing FIFO.
3
0 = DMA Mode 0
1 = DMA MOde 1
5:4
Sets the trigger level for the TX FIFO:
00 – 8 spaces
01 – 16 spaces
10 – 32 spaces
11 – 56 spaces
7:6
Sets the trigger level for the RX FIFO:
00 – 8 characters
01 – 16 characters
10 – 56 characters
11 – 60 characters
NOTE: FCR[5 – 4] can only be modified and enabled when EFR[4] is set. This is because the transmit trigger level is regarded as an enhanced
function.
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