TL16C752B-EP Datasheet, PDF (24/35 Pages) Texas Instruments – 3.3-V DUAL UART WITH 64-BYTE FIFO

TL16C752B-EP
3.3-V DUAL UART WITH 64-BYTE FIFO
SGLS153 – FEBRUARY 2003
PRINCIPLES OF OPERATION
Table 8 lists and describes the TL16C752B-EP internal registers.
Table 8. TL16C752B-EP Internal Registers
Addr REGISTER BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
READ/
WRITE
000
RHR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Read
000
THR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Write
001
IER
0/CTS
0/RTS
0/Xoff
0/X Sleep Modem
Rx line
THR
Rx data Read/Write
interrupt interrupt
sleep
mode^†
status
status
empty available
enable^†
enable^†
mode^†
interrupt interrupt interrupt interrupt
010
FCR
Rx trigger Rx trigger
0/TX
0/TX
DMA
Resets
Resets Enables
Write
level
level
trigger
level^†
trigger
level^†
mode
select
Tx FIFO Rx FIFO FIFOs
010
IIR
FCR(0)
FCR(0)
0/CTS,
RTS^†
0/Xoff^†
Interrupt
priority
Bit 2
Interrupt
priority
Bit 1
Interrupt
priority
Bit 0
Interrupt
status
Read
011
LCR
DLAB and Break Sets parity Parity type Parity Number of Word
Word Read/Write
EFR
control bit
select
enable stop bits length
length
enable
100
MCR
1x or 1x/4 TCR and 0/Xon Any 0/Enable
IRQ
FIFO Rdy
RTS
clock
TLR
loopback enable
enable
enable
OP
DTR Read/Write
101
LSR
0/Error in THR and
THR
Break
Framing
Parity
Overrun Data in
Read
Rx FIFO TSR empty empty
interrupt
error
error
error
receiver
110
MSR
CD
RI
DSR
CTS
∆CD
∆RI
∆DSR
∆CTS
Read
111
SPR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0 Read/Write
000
DLL
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0 Read/Write
001
DLH
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8 Read/Write
010
EFR
Auto-CTS Auto-RTS Special
Enable S/W flow S/W flow S/W flow S/W flow Read/Write
character enhanced control
detect
functions^†
Bit 3
control
Bit 2
control
Bit 1
control
Bit 0
100
Xon1
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0 Read/Write
101
Xon2
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0 Read/Write
110
Xoff1
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0 Read/Write
111
Xoff2
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0 Read/Write
110
TCR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0 Read/Write
111
TLR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0 Read/Write
111 FIFO Rdy
0
0
RX FIFO RX FIFO
0
B status A status
0
TX FIFO TX FIFO
B status A status
† _{The shaded bits in the above table can only be modified if register bit EFR[4] is enabled, i.e., if enhanced functions are enabled.}
NOTE: See the notes under Table 7 for more register access information.
Read
24
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