TL16C752B-EP Datasheet, PDF (21/35 Pages) Texas Instruments – 3.3-V DUAL UART WITH 64-BYTE FIFO

TX (A–B)
INT (A–B)
IOW
TL16C752B-EP
3.3-V DUAL UART WITH 64-BYTE FIFO
Start
Bit
Data Bits (5–8)
SGLS153 – FEBRUARY 2003
Stop
Bit
Active
D0 D1 D2 D3 D4 D5 D6 D7
5 Data Bits
6 Data Bits
7 Data Bits
Parity
Bit
td13
Next
Data
Start
Bit
td12
Active
Tx Ready
td14
Active
TX (A–B)
IOW
D0–D7
TXRDY (A–B)
16 Baud Rate Clock
Figure 18. Transmit Timing
Start
Bit
Data Bits (5–8)
Stop
Bit
D0 D1 D2 D3 D4 D5 D6 D7
Parity
Bit
Active
Next
Data
Start
Bit
Byte 1
td17
Active
Transmitter Ready
Figure 19. Transmit Ready Timing in Non-FIFO Mode
td18
Transmitter
Not Ready
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