LM3S828 Datasheet, PDF (238/526 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

General-Purpose Input/Outputs (GPIOs)
Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410
The GPIOIM register is the interrupt mask register. Bits set to High in GPIOIM allow the corresponding
pins to trigger their individual interrupts and the combined GPIOINTR line. Clearing a bit disables
interrupt triggering on that pin. All bits are cleared by a reset.
GPIO Interrupt Mask (GPIOIM)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
Offset 0x410
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
IME
Type RO
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:8
7:0
Name
reserved
IME
Type
RO
R/W
Reset
0x00
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPIO Interrupt Mask Enable
The IME values are defined as follows:
Value Description
0 Corresponding pin interrupt is masked.
1 Corresponding pin interrupt is not masked.
238
June 18, 2012
Texas Instruments-Production Data