LM3S828 Datasheet, PDF (15/526 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

Stellaris^® LM3S828 Microcontroller
Register 28: Software Reset Control 0 (SRCR0), offset 0x040 ............................................................. 203
Register 29: Software Reset Control 1 (SRCR1), offset 0x044 ............................................................. 204
Register 30: Software Reset Control 2 (SRCR2), offset 0x048 ............................................................. 205
Internal Memory ........................................................................................................................... 206
Register 1: Flash Memory Address (FMA), offset 0x000 .................................................................... 212
Register 2: Flash Memory Data (FMD), offset 0x004 ......................................................................... 213
Register 3: Flash Memory Control (FMC), offset 0x008 ..................................................................... 214
Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 216
Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 217
Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 218
Register 7: USec Reload (USECRL), offset 0x140 ............................................................................ 220
Register 8: Flash Memory Protection Read Enable (FMPRE), offset 0x130 ......................................... 221
Register 9: Flash Memory Protection Program Enable (FMPPE), offset 0x134 .................................... 222
General-Purpose Input/Outputs (GPIOs) ................................................................................... 223
Register 1: GPIO Data (GPIODATA), offset 0x000 ............................................................................ 233
Register 2: GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 234
Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 235
Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................ 236
Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ 237
Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 238
Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................ 239
Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ................................................... 240
Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................ 241
Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................ 242
Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................ 244
Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................ 245
Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................ 246
Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C ......................................................... 247
Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................ 248
Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514 ........................................................... 249
Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................ 250
Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................ 251
Register 19: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 ....................................... 252
Register 20: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 ....................................... 253
Register 21: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 ....................................... 254
Register 22: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ...................................... 255
Register 23: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ....................................... 256
Register 24: GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 ....................................... 257
Register 25: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ....................................... 258
Register 26: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ...................................... 259
Register 27: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 .......................................... 260
Register 28: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 .......................................... 261
Register 29: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 .......................................... 262
Register 30: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC ......................................... 263
General-Purpose Timers ............................................................................................................. 264
Register 1: GPTM Configuration (GPTMCFG), offset 0x000 .............................................................. 276
Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004 ............................................................ 277
Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008 ............................................................ 279
June 18, 2012
15
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