LM3S828 Datasheet, PDF (145/526 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

Stellaris^® LM3S828 Microcontroller
4.3.4.1
4.3.4.2
4.3.4.3
considered. In addition, because the JTAG module has integrated ARM Serial Wire Debug, the
method for switching between these two operational modes is described below.
GPIO Functionality
When the microcontroller is reset with either a POR or RST, the JTAG port pins default to their JTAG
configurations. The default configuration includes enabling the pull-up resistors (setting GPIOPUR
to 1 for PB7 and PC[3:0]) and enabling the alternate hardware function (setting GPIOAFSEL to
1 for PB7 and PC[3:0]) on the JTAG pins.
It is possible for software to configure these pins as GPIOs after reset by writing 0s to PB7 and
PC[3:0] in the GPIOAFSEL register. If the user does not require the JTAG port for debugging or
board-level testing, this provides five more GPIOs for use in the design.
Caution – If the JTAG pins are used as GPIOs in a design, PB7 and PC2 cannot have external pull-down
resistors connected to both of them at the same time. If both pins are pulled Low during reset, the
controller has unpredictable behavior. If this happens, remove one or both of the pull-down resistors,
and apply RST or power-cycle the part.
It is possible to create a software sequence that prevents the debugger from connecting to the Stellaris
microcontroller. If the program code loaded into flash immediately changes the JTAG pins to their
GPIO functionality, the debugger may not have enough time to connect and halt the controller before
the JTAG pin functionality switches. This may lock the debugger out of the part. This can be avoided
with a software routine that restores JTAG functionality based on an external or software trigger.
Communication with JTAG/SWD
Because the debug clock and the system clock can be running at different frequencies, care must
be taken to maintain reliable communication with the JTAG/SWD interface. In the Capture-DR state,
the result of the previous transaction, if any, is returned, together with a 3-bit ACK response. Software
should check the ACK response to see if the previous operation has completed before initiating a
new transaction. Alternatively, if the system clock is at least 8 times faster than the debug clock
(TCK or SWCLK), the previous operation has enough time to complete and the ACK bits do not have
to be checked.
ARM Serial Wire Debug (SWD)
In order to seamlessly integrate the ARM Serial Wire Debug (SWD) functionality, a serial-wire
debugger must be able to connect to the Cortex-M3 core without having to perform, or have any
knowledge of, JTAG cycles. This is accomplished with a SWD preamble that is issued before the
SWD session begins.
The switching preamble used to enable the SWD interface of the SWJ-DP module starts with the
TAP controller in the Test-Logic-Reset state. From here, the preamble sequences the TAP controller
through the following states: Run Test Idle, Select DR, Select IR, Capture IR, Exit1 IR, Update IR,
Run Test Idle, Select DR, Select IR, Capture IR, Exit1 IR, Update IR, Run Test Idle, Select DR,
Select IR, and Test-Logic-Reset states.
Stepping through the JTAG TAP Instruction Register (IR) load sequences of the TAP state machine
twice without shifting in a new instruction enables the SWD interface and disables the JTAG interface.
For more information on this operation and the SWD interface, see the ARM® Debug Interface V5
Architecture Specification.
Because this sequence is a valid series of JTAG operations that could be issued, the ARM JTAG
TAP controller is not fully compliant to the IEEE Standard 1149.1. This is the only instance where
the ARM JTAG TAP controller does not meet full compliance with the specification. Due to the low
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