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General-Purpose Input/Outputs (GPIOs)
Table 7-4. GPIO Pad Configuration Examples
Configuration
GPIO Register Bit Value^a
AFSEL DIR
ODR
DEN
Digital Input (GPIO)
0
0
0
1
Digital Output (GPIO)
0
1
0
1
Open Drain Output
0
1
1
1
(GPIO)
Open Drain
1
X
1
1
Input/Output (I²C)
Digital Input (Timer
1
X
0
1
CCP)
Digital Output (Timer
1
X
0
1
PWM)
Digital Input/Output
1
X
0
1
(SSI)
Digital Input/Output
1
X
0
1
(UART)
a. X=Ignored (don’t care bit)
?=Can be either 0 or 1, depending on the configuration
PUR
?
?
X
X
?
?
?
?
PDR
?
?
X
X
?
?
?
?
DR2R
X
?
?
?
X
?
?
?
DR4R
X
?
?
?
X
?
?
?
DR8R
X
?
?
?
X
?
?
?
SLR
X
?
?
?
X
?
?
?
Table 7-5. GPIO Interrupt Configuration Example
Desired
Pin 2 Bit Value^a
Register
Interrupt
Event
7
6
5
4
Trigger
GPIOIS
0=edge
X
X
X
X
1=level
GPIOIBE
0=single
X
X
X
X
edge
1=both
edges
GPIOIEV 0=Low level,
X
X
X
X
or negative
edge
1=High level,
or positive
edge
GPIOIM
0=masked
0
0
0
0
1=not
masked
a. X=Ignored (don’t care bit)
3
X
X
X
0
2
0
0
1
1
1
X
X
X
0
0
X
X
X
0
7.5 Register Map
Table 7-6 on page 231 lists the GPIO registers. The offset listed is a hexadecimal increment to the
register’s address, relative to that GPIO port’s base address:
■ GPIO Port A: 0x4000.4000
■ GPIO Port B: 0x4000.5000
■ GPIO Port C: 0x4000.6000
■ GPIO Port D: 0x4000.7000
230
June 18, 2012
Texas Instruments-Production Data