LM3S828 Datasheet, PDF (224/526 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

General-Purpose Input/Outputs (GPIOs)
7.1 Block Diagram
Figure 7-1. GPIO Module Block Diagram
PA0
PA1
PA2
PA3
PA4
PA5
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
7.2
U0Rx
UART0
PE0
U0Tx
PE1
SSIClk
SSIFss
SSI
SSIRx
PD0
SSITx
PD1
U1Rx
PD2
UART1
U1Tx
PD3
CCP0 Timer0 CCP1
CCP2
Timer1 CCP3
TCK/SWCLK
PC0
I2CSCL
I²C
I2CSDA
TRST
TMS/SWDIO
JTAG
TDI
PC1
PC2
TDO/SWO
PC3
PC4
PC5
PC6
CCP5 Timer2 CCP4
PC7
Signal Description
GPIO signals have alternate hardware functions. Table 7-3 on page 225 lists the GPIO pins and their
analog and digital alternate functions. The AINx analog signals are not 5-V tolerant and go through
an isolation circuit before reaching their circuitry. These signals are configured by clearing the
corresponding DEN bit in the GPIO Digital Enable (GPIODEN) register and setting the corresponding
AMSEL bit in the GPIO Analog Mode Select (GPIOAMSEL) register. The digital alternate hardware
functions are enabled by setting the appropriate bit in the GPIO Alternate Function Select
(GPIOAFSEL) and GPIODEN registers and configuring the PMCx bit field in the GPIO Port Control
(GPIOPCTL) register to the numeric enoding shown in the table below. Note that each pin must be
programmed individually; no type of grouping is implied by the columns in the table.
Important: All GPIO pins are configured as GPIOs and tri-stated by default (GPIOAFSEL=0,
GPIODEN=0, GPIOPDR=0, GPIOPUR=0, and GPIOPCTL=0, with the exception of the
four JTAG/SWD pins (shown in the table below). A Power-On-Reset (POR) or asserting
RST puts the pins back to their default state.
Table 7-1. GPIO Pins With Non-Zero Reset Values
GPIO Pins
PA[1:0]
PA[5:2]
Default State
UART0
SSI0
GPIOAFSEL GPIODEN GPIOPDR GPIOPUR
1
1
0
0
1
1
0
0
GPIOPCTL
0x1
0x1
224
June 18, 2012
Texas Instruments-Production Data