LM3S828 Datasheet, PDF (11/526 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

Stellaris^® LM3S828 Microcontroller
List of Tables
Table 1.
Table 2.
Table 2-1.
Table 2-2.
Table 2-3.
Table 2-4.
Table 2-5.
Table 2-6.
Table 2-7.
Table 2-8.
Table 2-9.
Table 2-10.
Table 2-11.
Table 2-12.
Table 2-13.
Table 3-1.
Table 3-2.
Table 3-3.
Table 3-4.
Table 3-5.
Table 3-6.
Table 3-7.
Table 3-8.
Table 3-9.
Table 4-1.
Table 4-2.
Table 4-3.
Table 5-1.
Table 5-2.
Table 5-3.
Table 5-4.
Table 5-5.
Table 5-6.
Table 6-1.
Table 6-2.
Table 7-1.
Table 7-2.
Table 7-3.
Table 7-4.
Table 7-5.
Table 7-6.
Table 8-1.
Table 8-2.
Table 8-3.
Table 8-4.
Table 9-1.
Revision History .................................................................................................. 19
Documentation Conventions ................................................................................ 24
Summary of Processor Mode, Privilege Level, and Stack Use ................................ 45
Processor Register Map ....................................................................................... 46
PSR Register Combinations ................................................................................. 51
Memory Map ....................................................................................................... 59
Memory Access Behavior ..................................................................................... 61
SRAM Memory Bit-Banding Regions .................................................................... 63
Peripheral Memory Bit-Banding Regions ............................................................... 63
Exception Types .................................................................................................. 69
Interrupts ............................................................................................................ 70
Exception Return Behavior ................................................................................... 74
Faults ................................................................................................................. 75
Fault Status and Fault Address Registers .............................................................. 76
Cortex-M3 Instruction Summary ........................................................................... 78
Core Peripheral Register Regions ......................................................................... 82
Memory Attributes Summary ................................................................................ 85
TEX, S, C, and B Bit Field Encoding ..................................................................... 88
Cache Policy for Memory Attribute Encoding ......................................................... 89
AP Bit Field Encoding .......................................................................................... 89
Memory Region Attributes for Stellaris Microcontrollers .......................................... 89
Peripherals Register Map ..................................................................................... 90
Interrupt Priority Levels ...................................................................................... 109
Example SIZE Field Values ................................................................................ 137
JTAG_SWD_SWO Signals (48QFP) ................................................................... 141
JTAG Port Pins Reset State ............................................................................... 142
JTAG Instruction Register Commands ................................................................. 146
System Control & Clocks Signals (48QFP) .......................................................... 150
Reset Sources ................................................................................................... 151
Clock Source Options ........................................................................................ 155
Possible System Clock Frequencies Using the SYSDIV Field ............................... 156
System Control Register Map ............................................................................. 160
PLL Mode Control .............................................................................................. 172
Flash Protection Policy Combinations ................................................................. 207
Flash Register Map ............................................................................................ 211
GPIO Pins With Non-Zero Reset Values .............................................................. 224
GPIO Pins and Alternate Functions (48QFP) ....................................................... 225
GPIO Signals (48QFP) ....................................................................................... 225
GPIO Pad Configuration Examples ..................................................................... 230
GPIO Interrupt Configuration Example ................................................................ 230
GPIO Register Map ........................................................................................... 231
Available CCP Pins ............................................................................................ 265
General-Purpose Timers Signals (48QFP) ........................................................... 266
16-Bit Timer With Prescaler Configurations ......................................................... 268
Timers Register Map .......................................................................................... 275
Watchdog Timer Register Map ............................................................................ 302
June 18, 2012
11
Texas Instruments-Production Data