LM3S828 Datasheet, PDF (16/526 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

Table of Contents
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
GPTM Control (GPTMCTL), offset 0x00C ........................................................................ 281
GPTM Interrupt Mask (GPTMIMR), offset 0x018 .............................................................. 284
GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..................................................... 286
GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................ 287
GPTM Interrupt Clear (GPTMICR), offset 0x024 .............................................................. 288
GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 ................................................. 290
GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C ................................................ 291
GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 ................................................... 292
GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 .................................................. 293
GPTM TimerA Prescale (GPTMTAPR), offset 0x038 ........................................................ 294
GPTM TimerB Prescale (GPTMTBPR), offset 0x03C ....................................................... 295
GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... 296
GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 297
GPTM TimerA (GPTMTAR), offset 0x048 ........................................................................ 298
GPTM TimerB (GPTMTBR), offset 0x04C ....................................................................... 299
Watchdog Timer ........................................................................................................................... 300
Register 1: Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 304
Register 2: Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 305
Register 3: Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 306
Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 307
Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 308
Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 309
Register 7: Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 310
Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 311
Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 312
Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 313
Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. 314
Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 315
Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. 316
Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. 317
Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. 318
Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 319
Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 320
Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 321
Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 322
Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 323
Analog-to-Digital Converter (ADC) ............................................................................................. 324
Register 1: ADC Active Sample Sequencer (ADCACTSS), offset 0x000 ............................................. 334
Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004 ........................................................... 335
Register 3: ADC Interrupt Mask (ADCIM), offset 0x008 ..................................................................... 336
Register 4: ADC Interrupt Status and Clear (ADCISC), offset 0x00C .................................................. 337
Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010 ............................................................ 338
Register 6: ADC Event Multiplexer Select (ADCEMUX), offset 0x014 ................................................. 339
Register 7: ADC Underflow Status (ADCUSTAT), offset 0x018 ........................................................... 342
Register 8: ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020 ............................................. 343
Register 9: ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 ................................. 345
Register 10: ADC Sample Averaging Control (ADCSAC), offset 0x030 ................................................. 346
Register 11: ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040 ............... 347
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June 18, 2012
Texas Instruments-Production Data